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gmortimer20031
Guest

Tue Jan 26, 2016 11:05 pm   



I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

MTIA
Geoff

gmortimer20031
Guest

Wed Jan 27, 2016 2:58 am   



On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote:
Quote:
On 1/26/2016 4:05 PM, gmortimer20031 wrote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

Can you give me more of an idea of your experience designing hardware
and/or HDL?

I remember some years ago a software designer came here to ask for help
writing a hello world program in VHDL. He was a sharp guy but did the
usual thing of starting out writing like it was C code. It only took a
little help and he got his goal done. We were banging pretty hard on
him about thinking in terms of hardware rather than what he was used to.
In the end he showed us wrong and did a good job.

I don't have a go-to book to recommend, at least not until I understand
better your level of experience. If you have no experience it may be a
harder road than you realize.

One other thing, I have heard from some there is a weak link in the
connection between the ARM firmware and the FPGA fabric. He said the
tool to support that was very hard to use and understand.

--

Rick


Hi Rick, many thanks for the reply

I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface.

The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm!

Best regards
Geoff

rickman
Guest

Wed Jan 27, 2016 6:16 am   



On 1/26/2016 4:05 PM, gmortimer20031 wrote:
Quote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?


Can you give me more of an idea of your experience designing hardware
and/or HDL?

I remember some years ago a software designer came here to ask for help
writing a hello world program in VHDL. He was a sharp guy but did the
usual thing of starting out writing like it was C code. It only took a
little help and he got his goal done. We were banging pretty hard on
him about thinking in terms of hardware rather than what he was used to.
In the end he showed us wrong and did a good job.

I don't have a go-to book to recommend, at least not until I understand
better your level of experience. If you have no experience it may be a
harder road than you realize.

One other thing, I have heard from some there is a weak link in the
connection between the ARM firmware and the FPGA fabric. He said the
tool to support that was very hard to use and understand.

--

Rick

gmortimer20031
Guest

Wed Jan 27, 2016 6:58 am   



On Wednesday, 27 January 2016 03:46:43 UTC, rickman wrote:
Quote:
On 1/26/2016 7:58 PM, gmortimer20031 wrote:
On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote:
On 1/26/2016 4:05 PM, gmortimer20031 wrote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

Can you give me more of an idea of your experience designing hardware
and/or HDL?

I remember some years ago a software designer came here to ask for help
writing a hello world program in VHDL. He was a sharp guy but did the
usual thing of starting out writing like it was C code. It only took a
little help and he got his goal done. We were banging pretty hard on
him about thinking in terms of hardware rather than what he was used to.
In the end he showed us wrong and did a good job.

I don't have a go-to book to recommend, at least not until I understand
better your level of experience. If you have no experience it may be a
harder road than you realize.

One other thing, I have heard from some there is a weak link in the
connection between the ARM firmware and the FPGA fabric. He said the
tool to support that was very hard to use and understand.

--

Rick

Hi Rick, many thanks for the reply

I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface.

The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm!

I guess the upside is you can have two CPUs to handle all the work.
With a fairly large FPGA you can partition the firmware and HDL as you
choose. I know it is popular to run Linux on one CPU and real time code
on the other while pushing only the really hard real time stuff in the
FPGA.

So you have a background in hardware, just not in HDL. I am guessing
you are committed to VHDL because of others' preferences. I didn't have
too much trouble learning to code in VHDL other than the type
conversions. That is a lot easier with the signed and unsigned data
types in the numeric_std package. I virtually don't use
std_logic_vector anymore.

--

Rick


The RTOS/metal division is certainly popular but gross overkill for this project. It is hoped practically everything can be done in the PL - partly as a learning exercise. I need to capture input date with a precision ADC at 1 MHz, downsample to 20kHz through a FIR filter and then perform a 1024-point FFT on the resulting stream. I have it schemed out but had completely underestimated the amount of hand coding involved in sticking together the Xilinx IP! I feel a new career coming on!

I have some third-hand zynq experience, with a bunch who used MATLAB/Simulink to generate the code for the PL - no sign of any problem crossing the fabric to/from the ARMs. I will dig further, last thing I need at this point on the learning curve.

Best regards
Geoff

gmortimer20031
Guest

Wed Jan 27, 2016 7:22 am   



On Tuesday, 26 January 2016 21:05:50 UTC, gmortimer20031 wrote:
Quote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

MTIA
Geoff


BTW if you use signed/unsigned can you do things like compare a signal with a decimal value ('if (adc_count >= 17) then') and/or use shift operators (asl, sra etc.)?

gmortimer20031
Guest

Wed Jan 27, 2016 7:28 am   



On Wednesday, 27 January 2016 04:58:56 UTC, gmortimer20031 wrote:
Quote:
On Wednesday, 27 January 2016 03:46:43 UTC, rickman wrote:
On 1/26/2016 7:58 PM, gmortimer20031 wrote:
On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote:
On 1/26/2016 4:05 PM, gmortimer20031 wrote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

Can you give me more of an idea of your experience designing hardware
and/or HDL?

I remember some years ago a software designer came here to ask for help
writing a hello world program in VHDL. He was a sharp guy but did the
usual thing of starting out writing like it was C code. It only took a
little help and he got his goal done. We were banging pretty hard on
him about thinking in terms of hardware rather than what he was used to.
In the end he showed us wrong and did a good job.

I don't have a go-to book to recommend, at least not until I understand
better your level of experience. If you have no experience it may be a
harder road than you realize.

One other thing, I have heard from some there is a weak link in the
connection between the ARM firmware and the FPGA fabric. He said the
tool to support that was very hard to use and understand.

--

Rick

Hi Rick, many thanks for the reply

I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface.

The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm!

I guess the upside is you can have two CPUs to handle all the work.
With a fairly large FPGA you can partition the firmware and HDL as you
choose. I know it is popular to run Linux on one CPU and real time code
on the other while pushing only the really hard real time stuff in the
FPGA.

So you have a background in hardware, just not in HDL. I am guessing
you are committed to VHDL because of others' preferences. I didn't have
too much trouble learning to code in VHDL other than the type
conversions. That is a lot easier with the signed and unsigned data
types in the numeric_std package. I virtually don't use
std_logic_vector anymore.

--

Rick

The RTOS/metal division is certainly popular but gross overkill for this project. It is hoped practically everything can be done in the PL - partly as a learning exercise. I need to capture input date with a precision ADC at 1 MHz, downsample to 20kHz through a FIR filter and then perform a 1024-point FFT on the resulting stream. I have it schemed out but had completely underestimated the amount of hand coding involved in sticking together the Xilinx IP! I feel a new career coming on!

I have some third-hand zynq experience, with a bunch who used MATLAB/Simulink to generate the code for the PL - no sign of any problem crossing the fabric to/from the ARMs. I will dig further, last thing I need at this point on the learning curve.

Best regards
Geoff


BTW if you use signed/unsigned can you do things like compare a signal with a decimal value ('if (adc_count >= 17) then') and/or use shift operators (sla, sra etc.)?

rickman
Guest

Wed Jan 27, 2016 8:30 am   



On 1/26/2016 7:58 PM, gmortimer20031 wrote:
Quote:
On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote:
On 1/26/2016 4:05 PM, gmortimer20031 wrote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

Can you give me more of an idea of your experience designing hardware
and/or HDL?

I remember some years ago a software designer came here to ask for help
writing a hello world program in VHDL. He was a sharp guy but did the
usual thing of starting out writing like it was C code. It only took a
little help and he got his goal done. We were banging pretty hard on
him about thinking in terms of hardware rather than what he was used to.
In the end he showed us wrong and did a good job.

I don't have a go-to book to recommend, at least not until I understand
better your level of experience. If you have no experience it may be a
harder road than you realize.

One other thing, I have heard from some there is a weak link in the
connection between the ARM firmware and the FPGA fabric. He said the
tool to support that was very hard to use and understand.

--

Rick

Hi Rick, many thanks for the reply

I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface.

The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm!


I guess the upside is you can have two CPUs to handle all the work.
With a fairly large FPGA you can partition the firmware and HDL as you
choose. I know it is popular to run Linux on one CPU and real time code
on the other while pushing only the really hard real time stuff in the
FPGA.

So you have a background in hardware, just not in HDL. I am guessing
you are committed to VHDL because of others' preferences. I didn't have
too much trouble learning to code in VHDL other than the type
conversions. That is a lot easier with the signed and unsigned data
types in the numeric_std package. I virtually don't use
std_logic_vector anymore.

--

Rick

rickman
Guest

Wed Jan 27, 2016 8:30 am   



On 1/27/2016 12:28 AM, gmortimer20031 wrote:
Quote:
On Wednesday, 27 January 2016 04:58:56 UTC, gmortimer20031 wrote:
On Wednesday, 27 January 2016 03:46:43 UTC, rickman wrote:
On 1/26/2016 7:58 PM, gmortimer20031 wrote:
On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote:
On 1/26/2016 4:05 PM, gmortimer20031 wrote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

Can you give me more of an idea of your experience designing hardware
and/or HDL?

I remember some years ago a software designer came here to ask for help
writing a hello world program in VHDL. He was a sharp guy but did the
usual thing of starting out writing like it was C code. It only took a
little help and he got his goal done. We were banging pretty hard on
him about thinking in terms of hardware rather than what he was used to.
In the end he showed us wrong and did a good job.

I don't have a go-to book to recommend, at least not until I understand
better your level of experience. If you have no experience it may be a
harder road than you realize.

One other thing, I have heard from some there is a weak link in the
connection between the ARM firmware and the FPGA fabric. He said the
tool to support that was very hard to use and understand.

--

Rick

Hi Rick, many thanks for the reply

I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface.

The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm!

I guess the upside is you can have two CPUs to handle all the work.
With a fairly large FPGA you can partition the firmware and HDL as you
choose. I know it is popular to run Linux on one CPU and real time code
on the other while pushing only the really hard real time stuff in the
FPGA.

So you have a background in hardware, just not in HDL. I am guessing
you are committed to VHDL because of others' preferences. I didn't have
too much trouble learning to code in VHDL other than the type
conversions. That is a lot easier with the signed and unsigned data
types in the numeric_std package. I virtually don't use
std_logic_vector anymore.

--

Rick

The RTOS/metal division is certainly popular but gross overkill for this project. It is hoped practically everything can be done in the PL - partly as a learning exercise. I need to capture input date with a precision ADC at 1 MHz, downsample to 20kHz through a FIR filter and then perform a 1024-point FFT on the resulting stream. I have it schemed out but had completely underestimated the amount of hand coding involved in sticking together the Xilinx IP! I feel a new career coming on!

I have some third-hand zynq experience, with a bunch who used MATLAB/Simulink to generate the code for the PL - no sign of any problem crossing the fabric to/from the ARMs. I will dig further, last thing I need at this point on the learning curve.

Best regards
Geoff

BTW if you use signed/unsigned can you do things like compare a signal with a decimal value ('if (adc_count >= 17) then') and/or use shift operators (sla, sra etc.)?


A decimal value would be an integer data type and yes, you can compare
that directly with a signed/unsigned type using the numeric_std library.
Here is a link with a summary of numeric_std capabilities.

https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/

Doulos has a lot of summary info on many things including the VHDL 2008
which has many useful additions to the language. Highly recommended
that you use it if your tools support it. In some tools you need to
turn on 2008 support first.

https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/

--

Rick

Stef
Guest

Wed Jan 27, 2016 3:57 pm   



On 2016-01-26 gmortimer20031 wrote in comp.lang.vhdl:
Quote:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?


When I started on the Zynq, this blog was very helpfull:
https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-116-Test-Pattern/ba-p/678021

It's now at part 116 (or more). When I started it went to 50 or something.
Just start at the beginning (links are at the bottom of the above link).
I got my fpga + 2-core bare metal app up and running with this, but I did
have previous experience with fpga, vhdl, arm etc.

Nice thing about the zynq is that that you can split up your application
in 3 parts: sub-usec real time (fpga), 'normal' real time (one core) and
long calculations or other tasks (second core), without the need to
interrupt long tasks for real time stuff as this can be handled by the
other core. At least if your application is suitable for such a division.

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

War is never imperative.
-- McCoy, "Balance of Terror", stardate 1709.2

gmortimer20031
Guest

Thu Jan 28, 2016 8:59 pm   



On Wednesday, 27 January 2016 08:59:53 UTC, Stef wrote:
Quote:
On 2016-01-26 gmortimer20031 wrote in comp.lang.vhdl:
I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score.

Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)?

When I started on the Zynq, this blog was very helpfull:
https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-116-Test-Pattern/ba-p/678021

It's now at part 116 (or more). When I started it went to 50 or something..
Just start at the beginning (links are at the bottom of the above link).
I got my fpga + 2-core bare metal app up and running with this, but I did
have previous experience with fpga, vhdl, arm etc.

Nice thing about the zynq is that that you can split up your application
in 3 parts: sub-usec real time (fpga), 'normal' real time (one core) and
long calculations or other tasks (second core), without the need to
interrupt long tasks for real time stuff as this can be handled by the
other core. At least if your application is suitable for such a division.

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

War is never imperative.
-- McCoy, "Balance of Terror", stardate 1709.2


Hi Stef

I'm writing the software for this thing too, but I think one core will suffice - just needs to communicate over CAN, at a relatively slow rate, the results of the calculations.

Very nice to be able to dig into the hardware and see how it works.

Best wishes
Geoff

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