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Guest

Wed Nov 29, 2017 10:00 pm   



I read online about a new VHDL standard to be released soon, this year IIRC. Taking a look at the Working Group's site it almost seems like the release has been pushed back to 2020...

Is this correct? Or am I misreading the information?

(I'm asking because I'm "feeling out" a couple of projects that might use VHDL in the future [though perhaps not NEAR future] and would like to know if I should plan these to use the latest standard.)

Jim Lewis
Guest

Wed Nov 29, 2017 11:10 pm   



A quick status update on the VHDL standard. The working group (WG) finished the individual language change specifications in April/May time frame.

The document is currently being edited by our volunteer editor. Unfortunately the document is in Frame. Unfortunately the latest version of Frame has been unstable while the standard was edited. It crashed many times and introduced numerous random edits - like deleting every usage of the word "in". Unfortunately the corruptions were not caught immediately and it has been a tedious process correcting them.

We are expecting a completed document for review shortly and will be balloting the standard early 2018.

If you have ever wondered why VHDL standards take so long to develop it is because they are developed by volunteers. The more volunteers we get the faster we can work. It is that simple.

If you are reading this, there is no reason why you should not be participating. Our website is at: eda-twiki.org

Hence, if you want to volunteer, go to our website and send me an email. If you want to complain and you are not actively participating, just address an email to yourself :)

Will my vendor implement VHDL-2018? My expectation is if your vendor is serious about selling you tools or wanting you to use their tools (in the event they are free), they should be supporting the language you are using. The first step to having tool support is making sure your vendor knows you want them to implement it - they expect this - they call it marketing driven standards support.

Best Regards,
Jim Lewis
IEEE P1076 (VHDL) WG Chair

rickman
Guest

Thu Nov 30, 2017 1:29 am   



onewingedshark_at_gmail.com wrote on 11/29/2017 3:00 PM:
Quote:
I read online about a new VHDL standard to be released soon, this year IIRC. Taking a look at the Working Group's site it almost seems like the release has been pushed back to 2020...

Is this correct? Or am I misreading the information?

(I'm asking because I'm "feeling out" a couple of projects that might use VHDL in the future [though perhaps not NEAR future] and would like to know if I should plan these to use the latest standard.)


I don't think the status of the standard is as important as the status of
the tools you plan to use. While vendors are often part of the standards
process, their implementations are often far behind the issuance of the
standards updates. So even if the new VHDL standard is ratified next year,
you may find the tools don't implement much of the changes for another year
or more after that.

What is your timeline like?

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998


Guest

Thu Nov 30, 2017 3:32 am   



On Wednesday, November 29, 2017 at 2:11:03 PM UTC-7, Jim Lewis wrote:
Quote:
A quick status update on the VHDL standard. The working group (WG) finished the individual language change specifications in April/May time frame..

The document is currently being edited by our volunteer editor. Unfortunately the document is in Frame. Unfortunately the latest version of Frame has been unstable while the standard was edited. It crashed many times and introduced numerous random edits - like deleting every usage of the word "in". Unfortunately the corruptions were not caught immediately and it has been a tedious process correcting them.

We are expecting a completed document for review shortly and will be balloting the standard early 2018.

If you have ever wondered why VHDL standards take so long to develop it is because they are developed by volunteers. The more volunteers we get the faster we can work. It is that simple.


Not a problem; I'm already familiar w/ the volunteer-work standards as I'm coming from Ada (which is also volunteer-run).

Quote:

If you are reading this, there is no reason why you should not be participating. Our website is at: eda-twiki.org

Hence, if you want to volunteer, go to our website and send me an email.


I am interested in it, but I do have some doubts as I've not yet actually written *any* VHDL as yet. (OTOH, sometimes having a complete novice around can come in handy; kind of like having the 6-year old on your staff of advisers [to point out flaws in your foolproof plans] from the "Evil Overlord" list.)

Quote:

Will my vendor implement VHDL-2018? My expectation is if your vendor is serious about selling you tools or wanting you to use their tools (in the event they are free), they should be supporting the language you are using. The first step to having tool support is making sure your vendor knows you want them to implement it - they expect this - they call it marketing driven standards support.


As I mentioned, I don't yet actually have a vendor... but when I'm ready to buy in, I'm certainly going to ask about that.


Guest

Thu Nov 30, 2017 3:39 am   



On Wednesday, November 29, 2017 at 4:29:38 PM UTC-7, rickman wrote:
Quote:

What is your timeline like?


I don't have much of one currently, realistically thinking I'd be lucky to get everything worked out and ready to go in three or four years, because there's a *LOT* that's "up in the air" right now.

Unrealistically, there's some stuff I could do now in the form of starting up some open-source projects that could be usable within what I'd really like to do w/ VHDL... but I've not had any luck in that arena (open-source).

Mark Curry
Guest

Thu Nov 30, 2017 6:18 pm   



In article <e461594c-7555-48be-80d0-97a6efc4940a_at_googlegroups.com>,
Jim Lewis <jim_at_synthworks.com> wrote:
Quote:

If you have ever wondered why VHDL standards take so long to develop it is because they are developed by volunteers. The
more volunteers we get the faster we can work. It is that simple.

If you are reading this, there is no reason why you should not be participating. Our website is at: eda-twiki.org

Hence, if you want to volunteer, go to our website and send me an email. If you want to complain and you are not actively
participating, just address an email to yourself Smile


Jim - A very big thanks for the link to eda-twiki.org. I'm a verilog user
lurking in this VHDL newsgroup. I'd been following along with the
SystemVerilog standardization for years - but then noticed that the entire
SystemVerilog working group discussions were completely gone from the
internet. No amount of googling on my part could find the reflector
archives. The Wayback machine only captured a few hit and miss threads.

It looks some of the reflector archives are making its way to this twiki
page. There's a link for the Pre-2016 archives - but currently leads to
a dead end. I'm hoping that the link is eventually fixed.

Thanks again.

Mark


Guest

Wed Dec 20, 2017 7:08 pm   



On Wednesday, November 29, 2017 at 2:11:03 PM UTC-7, Jim Lewis wrote:
Quote:

If you are reading this, there is no reason why you should not be participating. Our website is at: eda-twiki.org

Hence, if you want to volunteer, go to our website and send me an email. If you want to complain and you are not actively participating, just address an email to yourself Smile


E-mail (to edatwikiad) sent.

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