On Tuesday, May 5, 2020 at 10:46:44 AM UTC-4, jla...@highlandsniptechnology..com wrote:
On Tue, 5 May 2020 10:34:50 -0400, Phil Hobbs
On 2020-04-28 20:36, jlarkin_at_highlandsniptechnology.com wrote:
On Wed, 29 Apr 2020 02:15:39 +0530, Pimpom <nobody_at_nowhere.com> wrote:
On 4/29/2020 1:40 AM, John Larkin wrote:
This is a wonderful program. Looks like a few nice tweaks in this
No license, no email, no dongle.
Nice. I've been using online calculators with a much more limited
range of functions - mostly track resistance, temperature rise,
etc. Normally I save the whole webpage and tweak it to get rid of
all extraneous stuff.
Thanks for sharing.
I've got a differential PECL pair on the bottom of my board, with five
pickoffs to line receivers on the top, 1" apart, with two vias per
pickoff. The capacitances load the line and drag down the impedance.
Saturn calculates the via capacitances, and then I add the chip
So I can model the transmission line segments in LT Spice, with the
periodic capacitive loads, and look at the step response and timing
all along the line. I might skinny-up the traces to account for the
lumped loading, or futz the terminations, or something.
Saturn also calculates exotic transmission line impedances, like
Does your board house always use the same flavour of FR-4? Different
varieties range from at least 3.8 to 4.5, which can make a bit of a mess
We use several board houses, and we specify "FR4". We don't specify
impedances, which is expensive. 3.8 to 4.5 is about 4.15 +-10%, which
doesn't matter for digital stuff. The bigger issue is dielectric
Driver impedances and via capacitances are added variables on a trace,
and we can't analyze all of that.
I routinely include TDR test traces and usually come in a little low,
as low as 44ish for a 50 ohm trace. That's fine for digital stuff. If
something is just 1/0, it's usually OK. If it's jitter sensitive, it
needs more attention, especially for crosstalk, and slow edges on long
Analog or < 100 ps on FR4: keep it short.
I remember when the Xilinx Spartan 3 came out there were issues with the I/Os and the solution promoted by Xilinx reps in c.a.FPGA was to do a full SI simulation and analysis of traces to prevent damage from over and under voltage. I don't know off the top of my head what voltage levels to expect from 44 ohm traces but I suspect you aren't terminating your digital traces anyway, so hard say without knowing trace topologies and driver details.
I remember the "old" days of 5 volt TTL circuits that had trouble working at 25 MHz because of SI issues that few had insight into. I was barely an engineer at the time and had not even heard of SI. My next job was working on a 100 MFLOPS supercomputer. That machine had several system issues because the designers didn't understand how to maintain timing across a backplane much less between backplanes. Interesting transition.