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New invention: Systematic method of coding wave pipelined ci

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Weng Tianxiang
Guest

Sun Mar 22, 2015 12:23 am   



On Friday, March 13, 2015 at 10:45:11 PM UTC-7, Weng Tianxiang wrote:
Quote:
On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote:
On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote:
On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrote:
On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote:
Hi Jim, glen, JK, rickman, Mike, Andy,

I have filed a provisional patent application: "Systematic method of coding wave pipelined circuits in HDL". If it is proved correct, the patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four source code modules for a new library in HDL and thoroughly resolve a pending problem so that every digital designer can code wave-pipelined circuits in HDL.

Here is the abstract of the invention:

The present invention classifies all critical paths into two basic types: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: a static logic part, called critical path component (CPC), and a dynamic logic part, formalized into four wave-pipelining components (WPC) shared by all wave-pipelined circuits. Each wave-pipelining ready code in HDL comprises two components: a WPC instantiation and a CPC instantiation wire-connected and linked by a new link statement. Each WPC has new wave constants which play the same role as generic constants do, but whose initial values are determined and assigned by a synthesizer after code analysis, so designers can use after-synthesization information in their code before synthesization for wave-pipelining technology. The responsibility of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL is shifted from designers to synthesizers.

Anyone who are interested in its content is welcome to send a email request to the following email address: wtx wtx @ gmail . com with title "Systematic" and he will receive the full documents: one specification, 9 drawings and one text file in VHDL.

If one reviews the files and feels that it would be a good thing to recommend the application to his company to buy it, the first person to do it after his recommended company does so will receive $10,000 commission fee.

Thank you.

Weng

Hi,
I want to add some introductions to what the wave-pipelined circuits are and their status.

[0003] A synchronous digital system contains a lot of registers. Valid data flow through successive registers from system input registers to system output registers. All data flows are synchronous with triggering edges of a chip clock. For example, data flow from registers A to registers B, from registers B to registers C and so on in a successive order on the same clock cycle.
[0004] A path in a synchronous digital system is a route between any neighboring registers connected by combinational logic. If the target running frequency for a digital design is predetermined, the upper limit of propagating time for any paths is determined and has the inverse value of the target running frequency. A path is called a critical path if the time signals take to propagate through it is beyond the predetermined propagating time, and the time is called the path's critical time. If there are any critical paths, digital designers must spend time reducing all critical times by all means and eliminating all critical paths to meet the target running frequency.
[0005] Wave-pipelining is a technology which completes an operation that needs several clock cycles to propagate without intermediate registers and with input data acceptable on every clock cycle. For example, in a conventional pipelining operation, data flow from registers A to registers D through registers B and C to divide the critical path time into multiple smaller intervals to meet the critical time: A to B to C to D; with wave-pipelining, data flow through registers A and D without intermediate registers B and C. Absolutely, wave-pipelining will reduce logic resource usage and is superior to the conventional pipelining technology if it can be used.

Here are the most important inequalities involving wave-pipelining from paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burleson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no. 3, pp. 464-474, Sep. 1998.

[0018] Currently many memory chip manufacturers successfully use wave-pipelining in their memory chip products with higher rate outputs, reduced power consumption and logic resources; and a few scientists use FPGA chips as a base to show some circuits can be done with wave-pipelining in isolated environments. Their works prove that the wave-pipelining is a very powerful tool to reduce power consumption and logic resources. Now there are two major existing obstacles preventing any ordinary digital designers from using the wave-pipelining in HDL:
* The software algorithms making wave-pipelining successful, like Wong and Klass algorithms and others, have already been developed and matured, but ordinary digital designers have no means or resources to access to the technology, because there are no international HDL standards on how synthesizer manufacturers incorporate those capabilities into their products.
* HDL needs the capabilities for digital designers to write wave-pipelining ready code for any number of critical paths on a design-wide or chip-wide scale instead of in an isolated environment and the written code can be identified, synthesized and used to generate wave-pipelined circuits by any synthesizer in ASIC or FPGA, and they should be part of HDL standards..
[0019] The target of the present invention is:
* Invent a wave-pipelining coding system as new part of HDL standards for designers to write wave-pipelining ready code which can be identified, synthesized and used to generate wave-pipelined circuits by any synthesizer in ASIC or FPGA.
* Make wave-pipelining ready code written based on the coding system working with no extra logic generated, compared with independently written wave-pipelined circuits, and with no code changes when switching from non-wave-pipelined mode to wave-pipelined mode or vice verse if all of wave-pipelining ready code meet wave-pipelining requirements.
* Shift burdens of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL from individual designers to synthesizer manufacturers.
[0020] If the coding system becomes new part of HDL standards all synthesizer manufactures will automatically be forced to implement all well-known wave-pipelining algorithms and techniques within their products, a competition will start for better implementations, making wave-pipelining technique available to every digital designer in HDL.

Weng

Here I add some contents of the invention:

Main idea behind the present invention

[0057] The most difficult part coding all types of wave-pipelined circuits on a design-wide scale in HDL is that a wave-pipelined circuit code always comprises two logic parts:
* A static logic part: it doesn't change if the number of series clock cycles through the circuit changes and is unique for each of wave-pipelined circuits.
* A dynamic logic part: it does change if the number of series clock cycles through the circuit changes and is the same for one of groups of wave-pipelined circuits.
[0058] Every wave-pipelined circuit has its own change rules and those changes are unknown to designers when they are writing code and will be known to a synthesizer only after it has analyzed the circuit.
[0059] The present invention classifies all critical paths into two basic types: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: one is static logic part and called critical path component (CPC); another is dynamic logic part and formalized into four wave-pipelining components (WPC) shared by all wave-pipelined circuits. Under the present invention each of standard wave-pipelining ready code in HDL comprises two components: a WPC instantiation and a CPC instantiation which are wire-connected and linked by a new concurrent link statement. Each of four WPC embodiments has a group of new type wave constant, which plays the same role as a generic constant does, but whose initial value is determined and assigned by a synthesizer after it has analyzed the linked CPC component under slow mode and target mode, respectively, so designers can use after-synthesization information in their code before synthesization in HDL for wave-pipelining technology. Following the instructions of the present invention creates a situation that digital designers can write wave-pipelining ready code in HDL and the responsibility of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL is shifted from individual designers to synthesizer manufacturers.

How the method works

[0060] The systematic method of coding wave-pipelined circuits in HDL comprises following ten parts:
1. Define five signals, one counter, one switch and one table that will be used when generating wave-pipelined circuits on a design-wide or chip-wide scale in HDL.
2. Define the interfaces of a CPC each of which encapsulates a critical path's static logic part.
3. Define and implement four WPC embodiments in HDL each of which is a critical path's dynamic logic part: a series_module, an input_delay_module, a multiple_copy_module1 and a multiple_copy_module2.
4. Define one new keyword wave and three new wave constants which provide a means to dynamically transfer after-synthesization information to designers' code before synthesization.
5. Define the methods of determining and searching for wave constant values of a known WPC instantiation under slow mode and target mode, respectively.
6. Define three versions of a concurrent link statement: link1, link2 and link3, and rules on how they are used.
7. Define the pairing rules between a WPC and a CPC.
8. Define how a digital designer prepares wave-pipelining ready code systematically.
9. Shift the responsibility of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL from individual designers to synthesizer manufacturers.
10. Define how four WPC embodiments are simulated and debugged under any of current versions of a synthesizer in HDL.
[0061] It is fair to put the burden of successfully generating wave-pipelined circuits based on wave-pipelining ready code squarely on synthesizer manufacturers' shoulder if all necessary information is passed to a synthesizer. For example, with tens of papers claiming that successful wave-pipelined circuits are implemented in FPGA chips in an isolated environment, it is the responsibility of FPGA synthesizers to be capable of generating those wave-pipelined circuits in a design-wide environment without designers' further involvements, a process similar for them to the task of generating a circuit with the highest running frequency and minimum used resources if possible for any normal digital design code.

Thank you for your reading.

Here are more contents.

Definitions of wave-pipelining component and critical path component

[0062] A design component is called a critical path component (CPC) if it is an entity (a term in VHDL-2002) in HDL and encapsulates the static logic part of a critical path which is to be wave-pipelined circuit. There are two types of CPCs:
• A series CPC: it encapsulates a series critical path’s static logic part.
• A feedback CPC: it encapsulates a feedback critical path’s static logic part.

[0063] A CPC also refers to a CPC instantiation when it will not be misunderstood. The required interfaces of both a series CPC and a feedback CPC are always the same. The combinational logic of a CPC may be located within or outside of the component and there is no limit on it.

[0064] A design component is called a wave-pipelining component (WPC) if it is an entity in HDL, provided by HDL in a new wave-pipelining system library and used to generate a critical path’s dynamic logic part, i.e., to generate output data valid signal and write enable signals to the input and output registers of a critical path.

[0065] There are three types of WPC:
• A series_module is used to connect to a series CPC with input data acceptable on every clock cycle.
• An input_delay_module is used to connect to a series or feedback CPC with input data acceptable on every one or more clock cycle.
• A multiple_copy_module1 or a multiple_copy_module2 is used to connect to multiple copied series or feedback CPCs with input data acceptable on every clock cycle.

[0066] A WPC also refers to a WPC instantiation when it will not be misunderstood. Later multiple_copy_module refers to either of multiple_copy_module1 and multiple_copy_module2.

A synthesizer’s new signals, switch and table

[0067] A synthesizer that is able of handling wave-pipelining needs six signals, one switch, one table and the table’s row index to help finish its job:
• A floating signal target_running_frequency: it is set up by a designer and the target running frequency under which a design finally runs.
• A bit signal generate_circuit: it is set up by a designer and its initial value is deasserted. A synthesizer will generate related circuit files for a design under slow mode for slow mode hardware testing if generate_circuit is asserted and no errors are detected after a synthesization, or will not otherwise. A synthesizer will always generate related circuit files for a design under target mode for target mode hardware testing if no errors are detected after a synthesization.
• A bit signal feedback_bit: it is set up by a synthesizer and its initial value is deasserted. Assert the bit if a CPC is being analyzed and determined to have feedbacks, and deassert it after the analysis is finished.
• A bit signal keep_target_circuit: it is set up by a designer and its initial value is deasserted. Assert the bit if a designer wants to keep all CPC new circuits automatically and successfully modified by a synthesizer under target mode unchanged under slow mode when he is switching to synthesize the same design from under target mode to under slow mode and the related code doesn’t change, or deassert it otherwise. The bit provides a method for a designer to check if the new automatically and successfully modified circuits by a synthesizer don’t change basic logic..
• An integer signal parent_series_clock_number: it is set up by a synthesizer and Its initial value is zero. When the instantiation of a WPC delay_input_module or multiple_copy_module is being analyzed and executed its series_clock_number value is stored in parent_series_clock_number, and it is cleared to zero when the execution is finished.
• An integer signal start_number: it is set up by a synthesizer and used when the synthesizer determines that a CPC cannot meet the wave-pipelining requirements with input data acceptable on every clock cycle and the CPC is linked with a WPC input_delay_module or multiple_copy_module. The start_number is made equal to 2 if a WPC multiple_copy_module is linked or to feedback_clock_number if a WPC input_delay_module is linked as the starting value of wave constant input_clock_number or multiple_copy_number.
• A bit switch running_mode: it is set up by a designer and it has two valid values with slow mode being its initial value:
o Slow mode: under slow mode a digital designer designs his code, a design is synthesized, simulated, and hardware tested under the following assumptions:
 Signals take one clock cycle to propagate through any of CPCs under slow running frequency.
 Any of CPCs has input data acceptable on every clock cycle.
 No multiple copied CPCs are generated.
o Target mode: under target mode a design is synthesized, simulated, hardware tested and finally runs under predetermined target running frequency, and its implementation is determined and generated by a synthesizer under the following assumptions:
 Signals take one or more clock cycle to propagate through any of CPCs as designed.
 Each of CPCs has input data acceptable on every one or more clock cycle as wave-pipelining ready code indicates and it is necessary.
 Multiple copied CPCs are generated as wave-pipelining ready code indicates and it is necessary.
• A wave constant signal table: it is generated and manipulated by a synthesizer and stores information about each linked pair of a CPC and a WPC; all wave constant values and alias wave constant values can be accessed from the table.
• An integer row_index to the wave constant signal table: it is set up by a synthesizer and its initial value is 1. It is used as a row index for a new link statement in the wave constant signal table and will be increased by 1 after a synthesizer finishes the filling of the row during the source code scanning.

Thank you for your reading.

Weng

Here are more contents. It shows how a complicated problem is resolved by creative ideas.


New keyword wave and wave constant in HDL

[0068] When writing wave-pipelining code, digital designers don’t know how many clock cycles signals need to propagate through a critical path, and to finish their jobs, it may take several working cycles for them manually to adjust their code to make a wave-pipelined circuit working. This method is not feasible on a design-wide or chip-wide scale, because a design may have 100 or more critical paths to be wave-pipelined circuits and there is no guarantee for designers to perfectly remember which is finished and which is not, and most importantly, synthesizers are left aside of the business of wave-pipelining, giving no help at all. One of obstacles using wave-pipelining in HDL is how to establish a communication channel between a synthesizer and digital designers to provide the following essential functions:

• How a designer can use after-synthesization information to write code for wave-pipelined circuits before they have been synthesized in HDL for wave-pipelining technology. This function is not necessary for successfully generating a wave-pipelined circuit, but beneficial to implement a complex one.

• If all pieces of wave-pipelining ready code are written, a design has passed simulations and/or hardware testing under slow mode perfectly, and a synthesizer certifies that all wave-pipelining requirements are met with input data acceptable on every one or more clock cycle and no errors are detected after a synthesization, then correct full design circuits can be generated under target mode and work as designed with no code change during the switching from slow mode to target mode or vice verse on a design-wide or chip-wide scale. This function is critical and essential for successfully generating all wave-pipelined circuits on a design-wide or chip-wide scale in HDL.

[0069] New keyword wave and three wave constants are introduced to resolve the problem. In the following listing characters in bold type are new suggested definitions based on VHDL-2002.

entity_declaration ::=
entity identifier is
entity_header
entity_declarative_part
[begin
entity_statement_part ]
end [ entity ] [ entity_simple_name ] ;

entity_header ::> [formal_generic_clause ]
[formal_port_clause ]

generic_clause ::= generic ( generic_list ) ;
generic_list ::= generic_interface_list
interface_list ::= interface_element { ; interface_element }
interface_element ::= interface_declaration

interface_declaration ::> interface_constant_declaration
|interface_wave_constant_declaration
| interface_signal_declaration
| interface_variable_declaration
| interface_file_declaration

interface_constant_declaration ::> [constant] identifier_list : [ in] subtype_indication [ := static_expression ]

interface_wave_constant_declaration ::> wave [constant] wave_constant_list : [ in ] subtype_indication
[ := static_expression ]

wave_constant_list ::=
wave_constant_element { , wave_constant_element }

wave_constant_element ::=
wave_constant
|internal_wave_constant

wave_constant ::> series_clock_number
| input_clock_number
| multiple_copy_number

internal_wave_constant ::= one_hot

entity_declarative_part ::> { entity_declarative_item }

entity_declarative_item ::> subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration
| alias_wave_constant_declaration
| signal_declaration
|shared_variable_declaration
| file_declaration
| alias_declaration
| attribute_declaration
| attribute_specification
| disconnection_specification
| use_clause
| group_template_declaration
| group_declaration

architecture_body ::> architecture identifier of entity_name is
architecture_declarative_part
begin
architecture_statement_part
end[ architecture ] [ architecture_simple_name ] ;

architecture_declarative_part ::> { block_declarative_item }

block_declarative_item ::> subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration
| alias_wave_constant_declaration
| signal_declaration
| shared_variable_declaration
| file_declaration
| alias_declaration
| component_declaration
| attribute_declaration
| attribute_specification
| configuration_specification
| disconnection_specification
| use_clause
| group_template_declaration
| group_declaration

constant_declaration ::> constant identifier_list : subtype_indication [ := expression ] ;

alias_wave_constant_declaration ::> wave [ constant ] alias_wave_constant_list : subtype_indication :=
wave_constant ;

alias_wave_constant_list ::> alias_wave_constant { , alias_wave_constant }

alias_wave_constant ::= identifier

[0070] The set of following rules is called wave constant mechanism:

• There are three wave constants related to wave-pipelining technique: series_clock_number, input_clock_number and multiple_copy_number.

• A wave constant can only be declared in the generic_clause of the entity definition of a WPC embodiment, plays the same role as a generic constant declared in the same place does except that it has actual initial value 1 under slow mode, and actual initial value equal to or greater than 1 determined and assigned by a synthesizer under target mode, and the static expression in an interface wave constant declaration is always ignored.

• A WPC instantiation must not include corresponding association element with a formal wave constant in the generic map aspect.

• Any wave constant declared in a WPC definition is accessible by designers through an alias wave constant declaration.

• An alias wave constant declaration identifies a list of alias wave constants which are assigned a wave constant. Each alias wave constant must be linked with a WPC instantiation through a link statement and shares the wave constant value of the linked WPC instantiation for testing, debugging or implementing purpose. An alias wave constant plays the same role as a normal constant declared in the same place does.

• A CPC may have any of its linked WPC’s wave constants and output signals as its own input signal, but must have no input signals which are related to any unrelated WPC instantiation’s wave constants.

• The internal wave constant one_hot is used internally by a synthesizer to optimize the implementation of a WPC and not accessible by designers.

• A synthesizer has its discretion to determine internal wave constant one_hot value based on the environment and the consideration of its production technique used unless a WPC input_delay_module has its R_O output connected in which case one_hot will be ‘1’ in order to generate valid R_O output signal.


Thank you for your reading.

Weng


Wave-pipelining component series_module (SM) in HDL

[0071] FIG. 3 is the interface of a WPC embodiment series_module (SM) linked with a series CPC in FIG. 3A. CLK, RESET and SINI are three standard input signals for a synchronous component and the same for each of four WPCs, and play the same roles. CLK is clock source of the CPC. RESET is a global asynchronous initialization input signal. SINI is a global synchronous initialization input signal. Either of RESET/SINI is used to initialize a SM and one of them must be asserted once to keep SM in initial working status before it is used. One of RESET/SINI is necessary and another is optional, and if one of RESET/SINI is not used, it must be connected to ‘0’ to make it optimized out.

[0072] FIG. 3 has two additional input signals and three output signals:
• Input signal INI is designed to load initialization data into the linked series CPC. Input data at D_I for the linked CPC is initialization data if INI is asserted, or working input data otherwise. The assertion of input signal INI may last as long as needed. Input INI must be connected to ‘0’ or left opened with default value being ‘0’ if the linked CPC doesn’t need initialization data. Input signal INI must be asserted after one of RESET/SINI is asserted to make sure that SM is at the initial state, or wait for the series_clock_number of clock cycles to let the CPC go empty.
• Input signal WE_I drives write enable signal to the input registers of the linked CPC; input data at D_I of the linked CPC will be latched into the input registers of the CPC on the next clock cycle if WE_I is asserted on the current clock cycle, or will not otherwise.
• Output signal WE_O drives write enable signal to the output registers of the linked CPC; current arriving wave of combinational logic data will be latched into the output registers on the next clock cycle if WE_O is asserted on the current clock cycle, or will not otherwise.
• Output signal Valid_O is a data valid output signal; data at D_O of the linked CPC is valid if Valid_O is asserted or invalid otherwise.
• Output signal S_O is the Q outputs of each of internal right shift registers and may be useful when debugging or implementing a wave-pipelining ready code and optional. No extra logic will be generated if it is left opened without connection.

[0073] The assertion of each of WE_I, WE_O and Valid_O lasts one clock cycle for each valid input or output data, respectively.

[0074] FIG. 3A is the interface of a series CPC linked with a WPC series_module in FIG. 3. In addition to the global input signal CLK, the interface has four input signals and one output signal that are essential to wave-pipelining:
• Input signal INI is optional. If it exists, input data at D_I for the CPC is initialization data when INI is asserted, or working input data otherwise. The INI assertion may last as long as needed.
• Input signal WE_I is shared with the linked SM as write enable signal to the input registers.
• Input signal D_I is data input bus to the CPC.
• Input signal WE_O_I is write enable signal to the output registers of the CPC. It comes from the linked SM output signal WE_O and is used to latch current arriving wave of combinational logic data into output registers.
• Output signal D_O is output data bus. Output data at D_O is valid if output signal Valid_O of the linked SM is asserted, or invalid otherwise.

[0075] A CPC in FIG. 3A may have any number of additional input and output signals to assist the component and those signals are not drawn here. The dashed lines between FIG. 3 and FIG. 3A show how input and output signals of two components, a WPC SM and a series CPC, are connected. In addition to the connection of global clock signal CLK there are three connections between the two connected components:
• Input signals INI of both WPC and CPC are connected together if the CPC needs to load initialization data into it before working normally.
• Input signals WE_I of both components are connected.
• Output signal WE_O of SM in FIG. 3 drives write enable signal WE_O_I of its linked series CPC in FIG. 3A.

[0076] FIG. 4 is the schematics of a WPC embodiment series_module (SM) linked with a series CPC and with input data acceptable on every clock cycle.. 400 is a series CPC; 410 is the input registers of input data bus width; 420 is its combinational logic circuit; 430 is the output registers of output data width and input data bus width may be different from output data width. 440 is a SM linked with a series CPC 400 and comprises two sub-components: 450 is right shift registers with two or more bits; 460 is the right shift register controller and its schematics are shown in FIG. 4A. In FIG. 4 dotted line 470 represents the situations when signals take one clock cycle to propagate through the series CPC 400 under either slow mode or target mode; dashed lines represent the situations where the design runs under target mode and signals take X clock cycles to propagate through the series CPC 400 with X > 1. The dotted line 470 and dashed lines are mutually exclusive.

[0077] A SM is essentially right shift registers 450 with a variable length and its controller 460. The right shift registers have X+1 bits, where X is the number of series clock cycles for CPC 400. When a designer designs a series CPC or it runs under slow mode, signals are assumed to take one clock cycle to propagate through the component, X = 1 and the right shift registers have 2 bits; when the CPC runs under target mode, its number of series clock cycles is X, determined by a synthesizer, and the right shift registers have X+1 bits. S_O output signal is Q outputs of each bit register of the right shift registers 450 for possible debugging or implementing use and optional.

[0078] After either RESET or SINI input signal is asserted, the right shift registers are cleared immediately for RESET or on the next clock cycle for SINI. Each bit register of the right shift registers is connected together one after another with its Q output driving D input of next bit register with following exceptions:
• A 2-input and-gate A0 has one input coupled to input signal WE_I, another inversely coupled to input signal INI, and its output driving node W, D input of the most left bit register FFx and input W of controller 460..
• The Q output of second most right bit register drives output signal WE_O.
• The Q output of the most right bit register FF0 drives output signal Valid_O.

[0079] A linked pair of a SM and a CPC has two states based on input signal INI value if the CPC has INI input:
• Initial data loading state: When INI is asserted, node W is deasserted, leaving right shift registers 450 in an idle state. There will be no output data latched into the output registers FFo and output signal Valid_O will be deasserted. Initialization data will be latched into the input registers FFi through D_I on the next clock cycle if input signal WE_I is asserted on the current clock cycle.
• Working state: When INI is deasserted, working data will be latched into the input registers FFi through D_I on the next clock cycle if input signal WE_I is asserted on the current clock cycle; right shift registers 450 and its controller 460 are active, output signals WE_O, D_O and Valid_O work as designed.

[0080] In both situations input data will be acceptable on every clock cycle. Clock signal is not drawn in the present invention for clarity and simplicity.

[0081] FIG. 4A is the schematics of the right shift register controller 460 of a WPC series_module (SM). Or-gate OR1 has (X+2) input signals, where X is the number of series clock cycles, and under slow mode X = 1.
• Each of input signals Q0-Qx is driven by Q output of one bit register of the right shift registers, respectively, and the series CPC has valid data if one of Q0-Qx is asserted or invalid data otherwise.
• Input signal W is working input data ready signal. If input signal INI of a SM is asserted, W is deasserted; when input signal INI is deasserted, input signal W is equal to input signal WE_I of the SM.

[0082] Or-gate OR1 output signal E drives enable signal E to each bit register of the right shift registers 450. The right shift registers 450 will right shift one bit on next clock cycle if E is asserted on the current clock cycle or will not otherwise. Right shift registers 450 will right shift one bit on next clock cycle in either of two situations:
• There are valid data in the linked CPC.
• There is a working input data to enter the linked CPC.

[0083] Care must be taken before input signal INI is asserted if its CPC still contains valid data in it. In the situation the linked SM will continue to work to output internal valid data until it is empty, but the CPC may change its internal data flow if input signal INI to the CPC is asserted, contaminating the outgoing data. Of course, to people in the art the embodiment of right shift registers can be replaced by embodiment of left shift registers.

[0084] Based on connections of FIG. 3 and FIG. 3A a WPC series_module has nothing to do with input data at D_I and output data at D_O of its linked CPC, so series_module can handle any types of input data and output data of a series CPC and doesn’t have any overloading type.

Weng

KJ
Guest

Wed Mar 25, 2015 4:24 am   



On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote:
Quote:

Here I publish all source code for public confirmation.


What exactly would you like the public to confirm? Do you have made some specific claims?

Given that you have not claimed anything specific, I can only confirm the following:
- It does compile (Modelsim 10.3c)
- It does synthesize to something (Quartus 14.0; Top level entity=CPC1; 56 Max II logic elements)

Quote:

You may copy this part of code to do simulation by yourself.


Why would I want to simulate it?

Kevin Jennings

Daniel Kho
Guest

Wed Mar 25, 2015 12:45 pm   



On Friday, 6 March 2015 02:14:05 UTC+8, Weng Tianxiang wrote:
Quote:
Here is an example that MIT has 4 patents for HDTV and now it is suing a Japanese HDTV manufacturer.

MIT Sues Funai Over 4 HDTV Patents
http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents

Weng


The Japanese manufacturer is not a standard body. What was said earlier was that no standard body would want to be burgeoned by patents, IEEE included.

-dan

Weng Tianxiang
Guest

Sat Mar 28, 2015 1:16 pm   



On Wednesday, March 25, 2015 at 3:45:34 AM UTC-7, Daniel Kho wrote:
Quote:
On Friday, 6 March 2015 02:14:05 UTC+8, Weng Tianxiang wrote:
Here is an example that MIT has 4 patents for HDTV and now it is suing a Japanese HDTV manufacturer.

MIT Sues Funai Over 4 HDTV Patents
http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents

Weng


The Japanese manufacturer is not a standard body. What was said earlier was that no standard body would want to be burgeoned by patents, IEEE included.

-dan


-dan,
It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard.

Here is a Wikipedia website for your reference on how international standard body works.

http://en.wikipedia.org/wiki/3GPP

Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents:

http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html

Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents:

http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html

Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions.

Weng

Daniel Kho
Guest

Sun Mar 29, 2015 6:46 am   



On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote:
Quote:
-dan,
It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard..

Here is a Wikipedia website for your reference on how international standard body works.

http://en.wikipedia.org/wiki/3GPP

Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents:

http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html

Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents:

http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html

Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions.

Weng


That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents. If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented. In which case, the Chair will tell the whole group to not use that information in the standardization process. I think this is how it goes for most standard bodies.

-dan

Weng Tianxiang
Guest

Sun Mar 29, 2015 8:00 pm   



On Saturday, March 28, 2015 at 9:47:01 PM UTC-7, Daniel Kho wrote:
Quote:
On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote:
-dan,
It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard.

Here is a Wikipedia website for your reference on how international standard body works.

http://en.wikipedia.org/wiki/3GPP

Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents:

http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html

Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents:

http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html

Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions.

Weng


-dan


1. > That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents.

Agree.

2. > If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented.

Agree.

3. > In which case, the Chair will tell the whole group to not use that information in the standardization process.

Don't agree. You may ask current VHDL committee Chairman Jim Lewis what the by-law of VHDL is in the situation. He is closely watching the development of the issue now.

I remember he had recently mentioned in this group to organize a working group in VHDL to develop some patents for the VHDL committee.

4. > I think this is how it goes for most standard bodies.

Don't agree. Without patented inventions there would be no all G2, G3, G4 and G5 standards in cellphone and internet industries.

Weng

Quote:

-dan



Guest

Mon Mar 30, 2015 11:18 am   



On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote:
Quote:
On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote:

Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions.


That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents. If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented. In which case, the Chair will tell the whole group to not use that information in the standardization process. I think this is how it goes for most standard bodies.


See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page 4:

* The DASC will only accept patented material
under paragraph (a) of IEEE Patent Policy

Where paragraph (a) is found on PDF Page 2 (Slide #1):

a) A general disclaimer to the effect that the patentee will not enforce
any of its present or future patent(s) whose use would be required to
implement either mandatory or optional potions of the proposed IEEE
standard against any person or entity complying with the standard; or


The VASG P1076 effort falls under these conditions, no one is going to get rich on a standard essential patent required to implement the VHDL standard (nor either Verilog standards also under the auspices of DASC).

Also note Page 3 (slide #2):

Inappropriate Topics for IEEE WG Meetings
* Don't discuss licensing terms or conditions
...

Daniel Kho
Guest

Mon Mar 30, 2015 11:53 am   



On Monday, 30 March 2015 17:18:41 UTC+8, diog...@gmail.com wrote:
> The VASG P1076 effort falls under these conditions, no one is going to get rich on a standard essential patent required to implement the VHDL standard (nor either Verilog standards also under the auspices of DASC).

There goes... thanks Dio!

Weng Tianxiang
Guest

Tue Mar 31, 2015 5:31 pm   



On Tuesday, March 24, 2015 at 7:24:11 PM UTC-7, KJ wrote:
Quote:
On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote:

Here I publish all source code for public confirmation.


What exactly would you like the public to confirm? Do you have made some specific claims?

Given that you have not claimed anything specific, I can only confirm the following:
- It does compile (Modelsim 10.3c)
- It does synthesize to something (Quartus 14.0; Top level entity=CPC1; 56 Max II logic elements)


You may copy this part of code to do simulation by yourself.


Why would I want to simulate it?

Kevin Jennings


Here is how I claim to increase very-hard-implemented wave pipelined circuits to 100% successful rate.

The pairing rules between a WPC and a CPC

[0140] Here are the paring rules on how a WPC and a CPC are paired.

* A series CPC can be linked with one of four WPC embodiments:
o With a WPC series_module: Input data is acceptable on every clock cycle. If wave-pipelining requirements are not met, a designer has to either repeat the attempt with more CPC code modification, change code manually to make it linking with an input_delay_module or a multiple_copy_module, or quit the attempt otherwise.
o With a WPC input_delay_module: Input data is acceptable on every one or more clock cycle and its successful rate is 100%. If the number of input data clock cycles is large enough, there is at most only one wave of input data propagating through the CPC on any clock cycle and there are no wave-pipelining requirements any more.
o With a WPC multiple_copy_module: Input data is acceptable on every clock cycle and its successful rate is 100%. The cost may be the input registers and combinational logic copied multiple times if it is linked with a multiple_copy_module2, or the output registers may also be copied same times if it is linked with a multiple_copy_module1.

* A feedback CPC can be linked with one of three WPC embodiments:
o With a WPC input_delay_module: Input data is acceptable on every feedback or more clock cycles and its successful rate is 100%. If the number of input data clock cycles is large enough, there is at most only one wave of input data propagating through the CPC on any clock cycle, and there are no wave-pipelining requirements any more.
o With a WPC multiple_copy_module: Input data is acceptable on every clock cycle and its successful rate is 100%. The cost may be the input registers and combinational logic copied the number of feedback clock cycles or more times if it is linked with a multiple_copy_module2, or the output registers may also be copied same times if it is linked with a multiple_copy_module1.

[0141] A linked WPC input_delay_module or multiple_copy_module will degenerate to a WPC series_module if a synthesizer later finds that wave-pipelining requirements are met with one copy of the linked CPC and input data acceptable on every clock cycle, and there will be neither code change nor extra logic generated.

Weng

hssig
Guest

Wed Apr 01, 2015 4:48 pm   



Please spare us. I am so tired of reading your confusing and snotty postings.

Weng Tianxiang
Guest

Sat Apr 04, 2015 1:26 pm   



On Monday, March 30, 2015 at 2:18:41 AM UTC-7, diog...@gmail.com wrote:
Quote:
On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote:
On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote:

Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions.


That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents. If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented. In which case, the Chair will tell the whole group to not use that information in the standardization process. I think this is how it goes for most standard bodies.


See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page 4:

* The DASC will only accept patented material
under paragraph (a) of IEEE Patent Policy

Where paragraph (a) is found on PDF Page 2 (Slide #1):

a) A general disclaimer to the effect that the patentee will not enforce
any of its present or future patent(s) whose use would be required to
implement either mandatory or optional potions of the proposed IEEE
standard against any person or entity complying with the standard; or


The VASG P1076 effort falls under these conditions, no one is going to get rich on a standard essential patent required to implement the VHDL standard (nor either Verilog standards also under the auspices of DASC).

Also note Page 3 (slide #2):

Inappropriate Topics for IEEE WG Meetings
* Don't discuss licensing terms or conditions
...


-dio,
Thank you for your good information.

No matter whether or not I get rich through it, I will perfect my invented method to make contribution to science.

I will have another two successive patent applications about the same topics to publish in this group to perfect "the systematic method of coding wave pipelined circuits in HDL" so that it will be used universally in all modern 4-core processors someday, not mention in FPGA.

If someone is tired of reading new inventions, please stay away and you are not forced or flirted to read those "confusing and snotty" inventions.

Weng


Here are some important sections in my patent application:

New concurrent link statement in HDL

[0137] In order to let a synthesizer identify which code is a wave-pipelining ready code and help check the correctness of connections and paired type between a WPC instantiation and a CPC instantiation, three versions of new concurrent link statement are suggested to be introduced into HDL.

[0138] Here is the definition of new concurrent link statement in bold type based on VHDL-2002:

concurrent_statement ::block_statement
| link_statement
| process_statement
| concurrent_procedure_call_statement
| concurrent_assertion_statement
| concurrent_signal_assignment_statement
| component_instantiation_statement
| generate_statement

link_statement ::[ link_label : ] link_name ( wave_pipelining_component_label ,
critical_path_component_label [ , alias_wave_constant_list ] ) ;

link_label ::= label
link_name ::= link1 | link2 | link3

wave_pipelining_component_label ::= label

critical_path_component_label ::=
series_component_label
|input_delay_component_label
|multiple_copy_component_label

series_component_label ::= label
input_delay_component_label ::= label
multiple_copy_component_label ::= generate_label , copy_component_label
copy_component_label ::= label

label ::= identifier

[0139] The set of following rules is called link statement mechanism:

* Link1 statement links a WPC series_module instantiation with a series CPC instantiation and optional alias wave constants whose initial value is wave constant series_clock_number and which share the wave constant value of the linked WPC series_module.

* Link2 statement links a WPC input_delay_module instantiation with a series or a feedback CPC instantiation, and optional alias wave constants whose initial value is either wave constant series_clock_number or input_clock_number and which share the wave constant value of the linked WPC input_delay_module.

* Link3 statement links a WPC multiple_copy_module instantiation with a generate statement, a series or a feedback CPC instantiation, and optional alias wave constants whose initial value is either wave constant series_clock_number or multiple_copy_number and which share the wave constant value of the linked WPC multiple_copy_module.

* Wave_pipelining_component_label is the label marking the instantiation of a WPC series_module, input_delay_module or multiple_copy_module.

* Critical_path_component_label is the label marking a CPC instantiation.
o Series_component_label is the label marking the instantiation of a series CPC linked by a link1 statement.
o Input_delay_component_label is the label marking the instantiation of a series or a feedback CPC linked by a link2 statement.
o Multiple_copy_component_label contains two labels, the first one is generate_label marking a generate statement which generates multiple copied CPCs, the second is copy_component_label marking the instantiation of one of multiple copied series or feedback CPCs and linked by a link3 statement.

* Both wave_pipelining_component_label and critical_path_component_label must be located within the concurrent statement area of same architecture based on VHDL-2002, and can be referenced before they are defined in a link statement which is located in the same concurrent statement area.

* An alias wave constant must be visible to the link statement it involves.

* When a WPC multiple_copy_module is instantiated and linked with a generate statement through a link3 statement, the wave constant multiple_copy_number in the multiple_copy_module receives its new initial value through wave constant mechanism under slow mode and target mode, respectively, and the linked generate statement uses the wave constant multiple_copy_number constant value to generate 1 or more CPC under slow mode and target mode, respectively. The range used in the generate statement is fixed and must be from 0 to multiple_copy_number-1 or multiple_copy_number-1 downto 0.

The following several sections will not be published because it is related to synthesizing technology:

How a synthesizer determines wave constant values for a linked pair of a WPC and a CPC.

How a synthesizer gets wave constant values of a WPC under target mode.

How a synthesizer gets an alias wave constant value under target mode.

How a designer generates a successful wave-pipelined design in HDL.



Thank you for your patient reading.

Weng

KJ
Guest

Sun Apr 05, 2015 9:12 pm   



On Tuesday, March 31, 2015 at 11:31:35 AM UTC-4, Weng Tianxiang wrote:
Quote:
On Tuesday, March 24, 2015 at 7:24:11 PM UTC-7, KJ wrote:
On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote:

Here I publish all source code for public confirmation.


What exactly would you like the public to confirm? Do you have made some specific claims?

Given that you have not claimed anything specific, I can only confirm the following:
- It does compile (Modelsim 10.3c)
- It does synthesize to something (Quartus 14.0; Top level entity=CPC1; 56 Max II logic elements)


You may copy this part of code to do simulation by yourself.


Why would I want to simulate it?

Kevin Jennings

Here is how I claim to increase very-hard-implemented wave pipelined circuits to 100% successful rate.


Since you had requested 'public confirmation', the 'public' states that your claim can be refuted, not confirmed. Maybe you'll have better luck at USPTO. Then again, you may actually have a requirement now to disclose this thread to USPTO as being relevant background information regarding your proposed invention.

Kevin


Guest

Mon Apr 06, 2015 4:08 am   



On Thursday, April 2, 2015 at 3:48:44 AM UTC+13, hssig wrote:
> Please spare us. I am so tired of reading your confusing and snotty postings.

hssig -

Water off a ducks back. He didn't take the hint. It seems no matter how anyone attempts to discourage him he continues on like some dreary (in an Edgar Allan Poe sense) Energizer bunny.


Guest

Mon Mar 25, 2019 11:45 pm   



On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrote:
Quote:
Hi Jim, glen, JK, rickman, Mike, Andy,

I have filed a provisional patent application: "Systematic method of coding wave pipelined circuits in HDL". If it is proved correct, the patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four source code modules for a new library in HDL and thoroughly resolve a pending problem so that every digital designer can code wave-pipelined circuits in HDL.

Here is the abstract of the invention:

The present invention classifies all critical paths into two basic types: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: a static logic part, called critical path component (CPC), and a dynamic logic part, formalized into four wave-pipelining components (WPC) shared by all wave-pipelined circuits. Each wave-pipelining ready code in HDL comprises two components: a WPC instantiation and a CPC instantiation wire-connected and linked by a new link statement. Each WPC has new wave constants which play the same role as generic constants do, but whose initial values are determined and assigned by a synthesizer after code analysis, so designers can use after-synthesization information in their code before synthesization for wave-pipelining technology. The responsibility of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL is shifted from designers to synthesizers.

Anyone who are interested in its content is welcome to send a email request to the following email address: wtx wtx @ gmail . com with title "Systematic" and he will receive the full documents: one specification, 9 drawings and one text file in VHDL.

If one reviews the files and feels that it would be a good thing to recommend the application to his company to buy it, the first person to do it after his recommended company does so will receive $10,000 commission fee.


Did you ever get your patent? I'm curious.

--

Rick C.

-- Get a 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

Benjamin Couillard
Guest

Wed Mar 27, 2019 3:45 pm   



Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a écrit :
Quote:
On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrote:
Hi Jim, glen, JK, rickman, Mike, Andy,

I have filed a provisional patent application: "Systematic method of coding wave pipelined circuits in HDL". If it is proved correct, the patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four source code modules for a new library in HDL and thoroughly resolve a pending problem so that every digital designer can code wave-pipelined circuits in HDL.

Here is the abstract of the invention:

The present invention classifies all critical paths into two basic types: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: a static logic part, called critical path component (CPC), and a dynamic logic part, formalized into four wave-pipelining components (WPC) shared by all wave-pipelined circuits. Each wave-pipelining ready code in HDL comprises two components: a WPC instantiation and a CPC instantiation wire-connected and linked by a new link statement. Each WPC has new wave constants which play the same role as generic constants do, but whose initial values are determined and assigned by a synthesizer after code analysis, so designers can use after-synthesization information in their code before synthesization for wave-pipelining technology. The responsibility of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL is shifted from designers to synthesizers.

Anyone who are interested in its content is welcome to send a email request to the following email address: wtx wtx @ gmail . com with title "Systematic" and he will receive the full documents: one specification, 9 drawings and one text file in VHDL.

If one reviews the files and feels that it would be a good thing to recommend the application to his company to buy it, the first person to do it after his recommended company does so will receive $10,000 commission fee.

Did you ever get your patent? I'm curious.

--

Rick C.

-- Get a 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209


No grant so far...

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