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New coding method for a state machine in groups in HDL

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KJ
Guest

Sun Dec 01, 2019 12:46 am   



On Saturday, November 30, 2019 at 8:09:50 AM UTC-5, Weng Tianxiang wrote:
Quote:
The paper has a paragraph "4. Experiment Results" which uses their experiments to show it saves power.

Weng

And where are your experimental results that demonstrate something useful compared to current state of the art? That's all I've been asking...for years


Kevin

Richard Damon
Guest

Sun Dec 01, 2019 3:52 am   



On 11/30/19 1:40 PM, Rick C wrote:
Quote:
On Saturday, November 30, 2019 at 11:33:45 AM UTC-5, Richard Damon wrote:
On 11/30/19 9:55 AM, Rick C wrote:
On Saturday, November 30, 2019 at 9:16:40 AM UTC-5, Richard Damon wrote:

There are FPGAs which provide a 'gated clock' but they do the gating at
the row or region driver level, as that is where you get better power
savings (driving the clock tree is a significant use of power, while
gating at the flip-flop level saves virtually nothing, if it doesn't
cost you due to the extra logic, if it needs a LUT to gate, you have lost)

These gated clock drivers tend to have de-glitching logic on them that
makes them safe to use (gate signal low keeps the output clock from
going high but doesn't force a high output low). This says that you can
save power if you know a whole section won't be changing for awhile, but
unlikely helps on a small state machine that occasionally doesn't
change, as the power in the change prediction logic may cost more than
the savings. Also, since these clock drivers are a limited critical
resource, you likely don't have enough to use it fine grain.

Who makes these FPGAs? Are these in the typical clock generators most FPGAs have only a handful of? That's still better than no clock gating.


Microsemi, now part of Microchip. The gating is part of the regional
clock driving tree, so is somewhat limited, but not as limited as the
master clock generators (which also have gating).

Which products. I was just looking at their site the other day and I didn't see anything remotely new. Maybe I missed this? Or is this not new?


I use it in the SmartFusion2 and Igloo2 products. I don't think they
hype the feature, so you need to dig into the Macro Function Library
documentation and the Clocking Resources Documentation to see it. All
the global/row global clock buffers have an enable option.

Weng Tianxiang
Guest

Tue Dec 03, 2019 6:02 am   



Quote:
And where are your experimental results that demonstrate something useful compared to current state of the art? That's all I've been asking...for years

Kevin


KJ,

Why I don't like to directly answer your questions long time ago, for years, can be found in above question as another example, because your most questions are pointless and make nonsense as this question.

AS A PATENT, DO I NEED TO DO EXPERIMENTS TO DEMONSTRATE THAT MY CIRCUITS WOULD REDUCE POWER ASSUMPTION? A REALLY STUPID QUESTION!!!

As my first post shows that no one except me in the world who suggested or made any hits that any states in a state machine can be divided into groups AT ONE'S DISCRETION to reduce power consumption.

Here is a coding snippet for new method you can immediately understand what will happen for coding a state machine.

type State_Machine_t is (
First_group : (s1, s2, s3),
Second_Group : (s4, s5, s6),
Third_Group : (s7, s8, s9)
);
signal State_Machine, State_Machine_Next : State_Machine_t ;

You can carefully compare my patent with following paper and find what is the essential differences:

Here is a famous paper about the similar method with 244 cites, using probability theory to divide states into group:
http://www.scarpaz.com/2100-papers/Low%20Power/00503933.pdf

The 244 cites itself demonstrate that in academic circle it once was a hot issue and a very important issue.

I fully perfect the method with simplest method and simplest logic!

I not only invent the method, even though it is trivial, but I invent systematic methods on how to implement state division with a set of diagrams. The new systematic methods can be immediately implemented by any synthesizer manufacturers.

I divide all state jumping signals of a state group into 4 categories:

1. Local jumping signal which has its current state and next state within the state group and its current state is different from its target state;

2. Holding jumping signal which has its current state and next state within the state group and its current state is the same as its target state;

3. Entering jumping signal which has its current state not in the state group, but its next state is within the state group;

4. Leaving jumping signal which has its current state in the group, but its next state is not within the group.

The concept is so simple that every experienced designer except you, KJ, who knew the above concept would have ideas on how to generate all related state machine circuits.

Weng

KJ
Guest

Tue Dec 03, 2019 5:33 pm   



On Monday, December 2, 2019 at 11:02:59 PM UTC-5, Weng Tianxiang wrote:
Quote:
And where are your experimental results that demonstrate something useful compared to current state of the art? That's all I've been asking...for years



Why I don't like to directly answer your questions long time ago, for years, can be found in above question as another example, because your most questions are pointless and make nonsense as this question.

Two things can be concluded from this:
- When you make a claim but you have no evidence to support that claim, you consider the request to provide evidence to support your claim to be pointless and nonsense.
- You don't have any evidence to support your claims

This has been demonstrated to be true here on this thread and just about every other posting you've done in newsgroups in the past.

Quote:
AS A PATENT, DO I NEED TO DO EXPERIMENTS TO DEMONSTRATE THAT MY CIRCUITS WOULD REDUCE POWER ASSUMPTION? A REALLY STUPID QUESTION!!!
So if I was interested in purchasing the rights to your patent and I asked for your test results that back your claim of reduced power consumption before I would cut you a check, this is how you would respond. That speaks volumes.


You come to this newsgroup and comp.lang.vhdl typically spouting garbage. In a number of cases in the past I've shown your claims to be garbage by providing evidence that completely contradicts your claim. You ignore that evidence but can't refute it. When I ask for your test data that supports your claim, you go off on a rant like you've done here again, because you have nothing.

Why don't you find and post to some 'Snake Oil Salesman' newsgroup instead? Maybe there is a sub-group for rude salesman that would suit you. Looking here for a shill here isn't getting you anywhere.

You have nothing technical to back up anything you say here, and that is likely true for any of your patents as well.

Done with this thread with you. Good luck hawking your patents. You should probably hope that nobody searches your name and runs across your newsgroup postings.

Kevin Jennings

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