# New coding method for a state machine in groups in HDL

## Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - FPGA - New coding method for a state machine in groups in HDL

Goto page Previous  1, 2, 3  Next

Guest

Wed Nov 27, 2019 11:41 pm

On Monday, November 25, 2019 at 4:27:41 PM UTC-5, Weng Tianxiang wrote:
Quote:
Hi everyone,

Welcome all critics from ones who are interested in coding state machine that seems to many as matured, but can be further improved.

Here is a coding snippet for new method you can immediately understand what will happening for coding a state machine.

type State_Machine_t is (
First_group : (s1, s2, s3),
Second_Group : (s4, s5, s6),
Third_Group ; (s7, s8, s9)
);
signal State_Machine, State_Machine_Next : State_Machine_t ;

Here is only one sentence that tells you what you can do with new method:
Any state machine's states can be grouped together in coding in HDL at one's discretion and each group acts like a small state machine sharing a same initial state and all act together as coordinated as a full state machine..

Here is a famous paper about the method with 244 cites, using probability theory:
http://www.scarpaz.com/2100-papers/Low%20Power/00503933.pdf

But my patent describes a new simpler and perfect method using group theory:

Patent:10482208, "Coding and synthesizing a state machine in state groups"

https://patents.justia.com/search?q=tianxiang+weng

Thank KJ for helping me to improve the patent text.

Thank you.

Weng

Can you compare to this paper which divides states into groups and only activates clocks of active FSMs:

Asynchronous control of low-power gated-clock finite-state-machines

: ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems

An efficient approach to reduce power consumption in a synchronous Finite-State Machine (FSM) is to de-compose it, according to a partitioning algorithm, to a number of sub-FSMs that interact through some communication signals. Only one sub-FSM is clocked at a time and low power operation is obtained by only clocking the active sub-FSM. In this paper we introduce a new asynchronous communication control for the interacting sub-FSMs, which reduces the total capacitance switched by the system clock. Experimental results show that this leads to significant power savings when the FSM is partitioned into many sub-FSMs.

Weng Tianxiang
Guest

Thu Nov 28, 2019 12:26 am

Quote:
Can you compare to this paper which divides states into groups and only activates clocks of active FSMs:

Asynchronous control of low-power gated-clock finite-state-machines

: ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems

An efficient approach to reduce power consumption in a synchronous Finite-State Machine (FSM) is to de-compose it, according to a partitioning algorithm, to a number of sub-FSMs that interact through some communication signals. Only one sub-FSM is clocked at a time and low power operation is obtained by only clocking the active sub-FSM. In this paper we introduce a new asynchronous communication control for the interacting sub-FSMs, which reduces the total capacitance switched by the system clock. Experimental results show that this leads to significant power savings when the FSM is partitioned into many sub-FSMs.

Hi dhe,

Thank you for your post. I like your post very much because until now nobody cares about my working principles that are unique and inventive and many experienced designers can learn something from them.

From your post, I know at least 2 important differences between your post and my method so two methods work for the same function, but use two different principles.

1) Your post: a partitioning algorithm.
My method: partitioning method is at your discretion so you can partition a state machine freely.

2) Your post: a new asynchronous communication control for the interacting sub-FSMs.
My method: No new asynchronous communication control for the interacting sub-FSMs is generated except that only a few "or" and "and" operators are involved so that the logic is simpler than others.

I did not read and know the paper before until now.

Weng

Weng Tianxiang
Guest

Thu Nov 28, 2019 1:56 am

On Wednesday, November 27, 2019 at 2:26:15 PM UTC-8, Weng Tianxiang wrote:
Quote:
Can you compare to this paper which divides states into groups and only activates clocks of active FSMs:

Asynchronous control of low-power gated-clock finite-state-machines

: ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems

An efficient approach to reduce power consumption in a synchronous Finite-State Machine (FSM) is to de-compose it, according to a partitioning algorithm, to a number of sub-FSMs that interact through some communication signals. Only one sub-FSM is clocked at a time and low power operation is obtained by only clocking the active sub-FSM. In this paper we introduce a new asynchronous communication control for the interacting sub-FSMs, which reduces the total capacitance switched by the system clock. Experimental results show that this leads to significant power savings when the FSM is partitioned into many sub-FSMs.

Hi dhe,

Thank you for your post. I like your post very much because until now nobody cares about my working principles that are unique and inventive and many experienced designers can learn something from them.

From your post, I know at least 2 important differences between your post and my method so two methods work for the same function, but use two different principles.

1) Your post: a partitioning algorithm.
My method: partitioning method is at your discretion so you can partition a state machine freely.

2) Your post: a new asynchronous communication control for the interacting sub-FSMs.
My method: No new asynchronous communication control for the interacting sub-FSMs is generated except that only a few "or" and "and" operators are involved so that the logic is simpler than others.

I did not read and know the paper before until now.

Weng

Hi dlhe,

Sorry for misspelling your name in my last response to you.

The paper uses another paper's probability theory to generate group scheme.

Their method uses an asynchronous transition state machine to generate related clock gating signals and my method uses combination of state jumping signals to generate related clock gating signals.

Working principles of the present invention:
1) A piece of combinational logic is defined as a jumping signal for a state machine, and each jumping signal has the following characteristics:
a) A jumping signal has a current state.
b) A jumping signal has a target state.
c) A jumping signal has a transfer function that doesn’t include information of the state machine.
d) A jumping signal is deasserted if input signal SINI is asserted.
e) One and only one jumping signal is asserted on any cycle after the state machine is initialized.
f) If a jumping signal is asserted on the current cycle, the state machine will jump from the jumping signal’s current state to its target state on the next cycle.
2) All states are grouped into one or more State Groups (SGs) by a designer or a synthesizer, and an SG may have from one state to all states in the state machine.
3) Attach each of SGs with a clock gating device.
4) Define a jumping signal as a true jumping signal for an SG if the jumping signal’s current state and target state are different, and the target state belongs to the SG.
5) Feed each state of an SG with all true jumping signals whose target state is that state.
6) An SG will change states on the next cycle if the SG has at least one of the currently asserted jumping signal’s current state or target state, and the current state and the target state are 2 different states.
7) Generate a clock pulse to each of SGs on the next cycle when either input signal SINI is asserted on the current cycle or the SG will change states on the next cycle.

I copy this paragraph from my patent's specification.

Weng

Weng Tianxiang
Guest

Thu Nov 28, 2019 6:45 am

Quote:

Hi dhe,

Thank you for your post. I like your post very much because until now nobody cares about my working principles that are unique and inventive and many experienced designers can learn something from them.

From your post, I know at least 2 important differences between your post and my method so two methods work for the same function, but use two different principles.

1) Your post: a partitioning algorithm.
My method: partitioning method is at your discretion so you can partition a state machine freely.

2) Your post: a new asynchronous communication control for the interacting sub-FSMs.
My method: No new asynchronous communication control for the interacting sub-FSMs is generated except that only a few "or" and "and" operators are involved so that the logic is simpler than others.

I did not read and know the paper before until now.

Weng

Hi dlhe,

Sorry for misspelling your name in my last response to you.

The paper uses another paper's probability theory to generate group scheme.

Their method uses an asynchronous transition state machine to generate related clock gating signals and my method uses combination of state jumping signals to generate related clock gating signals.

Working principles of the present invention:
1) A piece of combinational logic is defined as a jumping signal for a state machine, and each jumping signal has the following characteristics:
a) A jumping signal has a current state.
b) A jumping signal has a target state.
c) A jumping signal has a transfer function that doesn’t include information of the state machine.
d) A jumping signal is deasserted if input signal SINI is asserted.
e) One and only one jumping signal is asserted on any cycle after the state machine is initialized.
f) If a jumping signal is asserted on the current cycle, the state machine will jump from the jumping signal’s current state to its target state on the next cycle.
2) All states are grouped into one or more State Groups (SGs) by a designer or a synthesizer, and an SG may have from one state to all states in the state machine.
3) Attach each of SGs with a clock gating device.
4) Define a jumping signal as a true jumping signal for an SG if the jumping signal’s current state and target state are different, and the target state belongs to the SG.
5) Feed each state of an SG with all true jumping signals whose target state is that state.
6) An SG will change states on the next cycle if the SG has at least one of the currently asserted jumping signal’s current state or target state, and the current state and the target state are 2 different states.
7) Generate a clock pulse to each of SGs on the next cycle when either input signal SINI is asserted on the current cycle or the SG will change states on the next cycle.

I copy this paragraph from my patent's specification.

Weng

Hi dlhe,

You may be confused by above description, here are more definitions which are bases for developing my method fully and systematically.

12) A jumping signal is defined as a true jumping signal for an SG if the jumping signal’s current state and target state are different, and its target state belongs to the SG.

13) A true jumping signal is called an entry jumping signal for an SG if the SG does not have the true jumping signal’s current state.

14) A true jumping signal is called a local jumping signal for an SG if the SG has the true jumping signal’s current state.

15) A jumping signal is called a leaving jumping signal for an SG if the SG has the jumping signal’s current state and does not have its target state.

16) A jumping signal is called a crossing jumping signal for a state machine if the jumping signal’s current state and target state belong to 2 different SGs.

17) A crossing jumping signal belongs to two SGs: a) the SG has the crossing jumping signal’s current state and the crossing jumping signal is used as a leaving jumping signal for the SG; and b) if the SG has the crossing jumping signal’s target state and the crossing jumping signal is used as an entry jumping signal for the SG.

1 A jumping signal is called a holding jumping signal for an SG if the SG has the jumping signal’s current state and target state, and both are the same.

19) An SG is said to have a currently asserted jumping signal on the current cycle if the currently asserted jumping signal belongs to the SG.

Using different combinations of all jumping signals belonging to a SG, one can generate different simplest circuits to finish the job.

Weng

KJ
Guest

Thu Nov 28, 2019 10:44 pm

> Using different combinations of all jumping signals belonging to a SG, one can generate different simplest circuits to finish the job.

For years now you've made these same claims about your state machines without providing any evidence to back the claim. During those years I've provided evidence showing your claims to be false. I doubt there will be anything different this time since it appears to be more of the same.

Kevin Jennings

Weng Tianxiang
Guest

Thu Nov 28, 2019 11:33 pm

On Thursday, November 28, 2019 at 12:44:48 PM UTC-8, KJ wrote:
Quote:
Using different combinations of all jumping signals belonging to a SG, one can generate different simplest circuits to finish the job.

For years now you've made these same claims about your state machines without providing any evidence to back the claim. During those years I've provided evidence showing your claims to be false. I doubt there will be anything different this time since it appears to be more of the same.

Kevin Jennings

KJ,

Please read my diagrams carefully in my patent and you are familiar with none of what I asked you to check my application for specification and diagrams 9 years ago.

If you can find any point, please show it and don't talk nothing.

I remember you were talking about some jumping signal generations last time and I didn't see any point of your argument.

Let HT-Lab or Rick as arbitrator to determine whether your standpoint is meaningless or not. Last time Rick was on my side.

Actually this patent, US 10482208, has nothing to do with how to generate jumping signals for a state machine!!!

I define the jumping signals for a state machine in the patent, but never mention how to generate them.

Weng

KJ
Guest

Sat Nov 30, 2019 12:03 am

On Thursday, November 28, 2019 at 4:33:59 PM UTC-5, Weng Tianxiang wrote:
Quote:
On Thursday, November 28, 2019 at 12:44:48 PM UTC-8, KJ wrote:

Please read my diagrams carefully in my patent and you are familiar with none of what I asked you to check my application for specification and diagrams 9 years ago.
I referenced and commented on the unsubstantiated claim you made in the posting you made in this newsgroup. You have not provided any evidence backing your statement.

Quote:

I remember you were talking about some jumping signal generations last time and I didn't see any point of your argument.
OK, but that speaks to your abilities.

Quote:

Let HT-Lab or Rick as arbitrator to determine whether your standpoint is meaningless or not. Last time Rick was on my side.

HAHAHA, we're choosing teams now???

Quote:

Actually this patent, US 10482208, has nothing to do with how to generate jumping signals for a state machine!!!
Who care what the patent has nothing to do about?

Kevin Jennings

Weng Tianxiang
Guest

Sat Nov 30, 2019 5:56 am

On Friday, November 29, 2019 at 2:03:41 PM UTC-8, KJ wrote:
Quote:
On Thursday, November 28, 2019 at 4:33:59 PM UTC-5, Weng Tianxiang wrote:
On Thursday, November 28, 2019 at 12:44:48 PM UTC-8, KJ wrote:

Please read my diagrams carefully in my patent and you are familiar with none of what I asked you to check my application for specification and diagrams 9 years ago.
I referenced and commented on the unsubstantiated claim you made in the posting you made in this newsgroup. You have not provided any evidence backing your statement.

I remember you were talking about some jumping signal generations last time and I didn't see any point of your argument.
OK, but that speaks to your abilities.

Let HT-Lab or Rick as arbitrator to determine whether your standpoint is meaningless or not. Last time Rick was on my side.

HAHAHA, we're choosing teams now???

Actually this patent, US 10482208, has nothing to do with how to generate jumping signals for a state machine!!!
Who care what the patent has nothing to do about?

Kevin Jennings

KJ,
On one side you said:
"I referenced and commented on the unsubstantiated claim you made in the posting you made in this newsgroup."

On other side you said:
"Who care what the patent has nothing to do about?"

Here are the facts:
1. It became patent US 10482208 since 11/19/2019.

2. If you can pinpoint any unsubstantiated claim from the official US patent, what you make may invalidate the patent.

3. I welcome your action and have no objection against it, because I believe the state machine's new coding method certainly will be accepted into HDL SOMEDAY, because it generates no burden for coding state machines and finally perfects the work made by a lot of papers one of which has 224 cites,
http://www.scarpaz.com/2100-papers/Low%20Power/00503933.pdf,
and every code designer will benefit on the new coding method.

Last time Rick and you were arguing against each other on your pointless points and I firmly stand with Rick, but I did not participate your argument, not because you are an expert and comments are valuable, but because your point is no sense and pointless in any way and I don't want to spend any time on your pointless points.

KJ, please be BRAVE to pinpoint WHICH PAGE, WHICH LINES 哦人WHICH FIGURES have any type of LOGIC and SIGNIFICANT errors.

If you do this I will response to your points immediately and let Rick and HT-Lab determine if your claim is pointless or not, otherwise I will ignore all your later posts on this subject.

9 (nine) years ago I asked you to help me to check the application text for grammar errors and I thank you for your help with paying.

Now it became a patent with all brand new figures and specifications you have never seen it before publication, and all figures, specification, claims for the patent were made by myself.

Weng

Andy Bennet
Guest

Sat Nov 30, 2019 10:24 am

On 30/11/2019 03:56, Weng Tianxiang wrote:
Quote:
On Friday, November 29, 2019 at 2:03:41 PM UTC-8, KJ wrote:
On Thursday, November 28, 2019 at 4:33:59 PM UTC-5, Weng Tianxiang wrote:
On Thursday, November 28, 2019 at 12:44:48 PM UTC-8, KJ wrote:

Please read my diagrams carefully in my patent and you are familiar with none of what I asked you to check my application for specification and diagrams 9 years ago.
I referenced and commented on the unsubstantiated claim you made in the posting you made in this newsgroup. You have not provided any evidence backing your statement.

I do not see how your re-arrangment of state machines saves power if
this is the fundamental goal.
In FPGA design it is a definate no-no to gate the clock signal into a
F/F, or indeed manufacture a clock signal from a logic expression which
will produce difficult to predict setup and hold times as well as glitches.
The power in a F/F is predominantly driven by the change of state of the
flip flop.
You should only 'gate' the clock into a F/F by using its enable control
line. The F/F remains continuously clocked, but the input of the flip
flop is controlled by the enable to either be the output of the flip
flop or new data.
This then gives predicatable setup and hold times and a glitch free
operation - assuming the enables are synchronous, which is basic design
practise.

AB

Weng Tianxiang
Guest

Sat Nov 30, 2019 3:09 pm

Quote:

I do not see how your re-arrangment of state machines saves power if
this is the fundamental goal.
In FPGA design it is a definate no-no to gate the clock signal into a
F/F, or indeed manufacture a clock signal from a logic expression which
will produce difficult to predict setup and hold times as well as glitches.
The power in a F/F is predominantly driven by the change of state of the
flip flop.
You should only 'gate' the clock into a F/F by using its enable control
line. The F/F remains continuously clocked, but the input of the flip
flop is controlled by the enable to either be the output of the flip
flop or new data.
This then gives predicatable setup and hold times and a glitch free
operation - assuming the enables are synchronous, which is basic design
practise.

AB

AB,

Good, a technical and basic question!!!

A F/F saves power if it does not receive clock pulse when its states do not change.

In my design a F/F input pin always has '0' input if it does not change states and I don't know if it saves power.

Please refer to this paper suggested by dlhe in his earlier post and my patent does not have to further explain it. I read the paper only after dlhe suggested and found the paper does many experiments to confirm how it saves power.

The paper has a paragraph "4. Experiment Results" which uses their experiments to show it saves power.

Weng

Asynchronous control of low-power gated-clock finite-state-machines

: ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems

An efficient approach to reduce power consumption in a synchronous Finite-State Machine (FSM) is to de-compose it, according to a partitioning algorithm, to a number of sub-FSMs that interact through some communication signals. Only one sub-FSM is clocked at a time and low power operation is obtained by only clocking the active sub-FSM. In this paper we introduce a new asynchronous communication control for the interacting sub-FSMs, which reduces the total capacitance switched by the system clock. Experimental results show that this leads to significant power savings when the FSM is partitioned into many sub-FSMs.

Richard Damon
Guest

Sat Nov 30, 2019 4:16 pm

On 11/30/19 3:24 AM, Andy Bennet wrote:
Quote:
On 30/11/2019 03:56, Weng Tianxiang wrote:
On Friday, November 29, 2019 at 2:03:41 PM UTC-8, KJ wrote:
On Thursday, November 28, 2019 at 4:33:59 PM UTC-5, Weng Tianxiang
wrote:
On Thursday, November 28, 2019 at 12:44:48 PM UTC-8, KJ wrote:

Please read my diagrams carefully in my patent and you are familiar
with none of what I asked you to check my application for
specification and diagrams 9 years ago.
I referenced and commented on the unsubstantiated claim you made in
the posting you made in this newsgroup.  You have not provided any

I do not see how your re-arrangment of state machines saves power if
this is the fundamental goal.
In FPGA design it is a definate no-no to gate the clock signal into a
F/F, or indeed manufacture a clock signal from a logic expression which
will produce difficult to predict setup and hold times as well as glitches.
The power in a F/F is predominantly driven by the change of state of the
flip flop.
You should only 'gate' the clock into a F/F by using its enable control
line. The F/F remains continuously clocked, but the input of the flip
flop is controlled by the enable to either be the output of the flip
flop or new data.
This then gives predicatable setup and hold times and a glitch free
operation - assuming the enables are synchronous, which is basic design
practise.

AB

There are FPGAs which provide a 'gated clock' but they do the gating at
the row or region driver level, as that is where you get better power
savings (driving the clock tree is a significant use of power, while
gating at the flip-flop level saves virtually nothing, if it doesn't
cost you due to the extra logic, if it needs a LUT to gate, you have lost)

These gated clock drivers tend to have de-glitching logic on them that
makes them safe to use (gate signal low keeps the output clock from
going high but doesn't force a high output low). This says that you can
save power if you know a whole section won't be changing for awhile, but
unlikely helps on a small state machine that occasionally doesn't
change, as the power in the change prediction logic may cost more than
the savings. Also, since these clock drivers are a limited critical
resource, you likely don't have enough to use it fine grain.

Rick C
Guest

Sat Nov 30, 2019 4:55 pm

On Saturday, November 30, 2019 at 9:16:40 AM UTC-5, Richard Damon wrote:
Quote:
On 11/30/19 3:24 AM, Andy Bennet wrote:
On 30/11/2019 03:56, Weng Tianxiang wrote:
On Friday, November 29, 2019 at 2:03:41 PM UTC-8, KJ wrote:
On Thursday, November 28, 2019 at 4:33:59 PM UTC-5, Weng Tianxiang
wrote:
On Thursday, November 28, 2019 at 12:44:48 PM UTC-8, KJ wrote:

Please read my diagrams carefully in my patent and you are familiar
with none of what I asked you to check my application for
specification and diagrams 9 years ago.
I referenced and commented on the unsubstantiated claim you made in
the posting you made in this newsgroup.  You have not provided any

I do not see how your re-arrangment of state machines saves power if
this is the fundamental goal.
In FPGA design it is a definate no-no to gate the clock signal into a
F/F, or indeed manufacture a clock signal from a logic expression which
will produce difficult to predict setup and hold times as well as glitches.
The power in a F/F is predominantly driven by the change of state of the
flip flop.
You should only 'gate' the clock into a F/F by using its enable control
line. The F/F remains continuously clocked, but the input of the flip
flop is controlled by the enable to either be the output of the flip
flop or new data.
This then gives predicatable setup and hold times and a glitch free
operation - assuming the enables are synchronous, which is basic design
practise.

AB

There are FPGAs which provide a 'gated clock' but they do the gating at
the row or region driver level, as that is where you get better power
savings (driving the clock tree is a significant use of power, while
gating at the flip-flop level saves virtually nothing, if it doesn't
cost you due to the extra logic, if it needs a LUT to gate, you have lost)

These gated clock drivers tend to have de-glitching logic on them that
makes them safe to use (gate signal low keeps the output clock from
going high but doesn't force a high output low). This says that you can
save power if you know a whole section won't be changing for awhile, but
unlikely helps on a small state machine that occasionally doesn't
change, as the power in the change prediction logic may cost more than
the savings. Also, since these clock drivers are a limited critical
resource, you likely don't have enough to use it fine grain.

Who makes these FPGAs? Are these in the typical clock generators most FPGAs have only a handful of? That's still better than no clock gating.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

Richard Damon
Guest

Sat Nov 30, 2019 6:33 pm

On 11/30/19 9:55 AM, Rick C wrote:
Quote:
On Saturday, November 30, 2019 at 9:16:40 AM UTC-5, Richard Damon wrote:

There are FPGAs which provide a 'gated clock' but they do the gating at
the row or region driver level, as that is where you get better power
savings (driving the clock tree is a significant use of power, while
gating at the flip-flop level saves virtually nothing, if it doesn't
cost you due to the extra logic, if it needs a LUT to gate, you have lost)

These gated clock drivers tend to have de-glitching logic on them that
makes them safe to use (gate signal low keeps the output clock from
going high but doesn't force a high output low). This says that you can
save power if you know a whole section won't be changing for awhile, but
unlikely helps on a small state machine that occasionally doesn't
change, as the power in the change prediction logic may cost more than
the savings. Also, since these clock drivers are a limited critical
resource, you likely don't have enough to use it fine grain.

Who makes these FPGAs? Are these in the typical clock generators most FPGAs have only a handful of? That's still better than no clock gating.

Microsemi, now part of Microchip. The gating is part of the regional
clock driving tree, so is somewhat limited, but not as limited as the
master clock generators (which also have gating).

Rick C
Guest

Sat Nov 30, 2019 8:40 pm

On Saturday, November 30, 2019 at 11:33:45 AM UTC-5, Richard Damon wrote:
Quote:
On 11/30/19 9:55 AM, Rick C wrote:
On Saturday, November 30, 2019 at 9:16:40 AM UTC-5, Richard Damon wrote:

There are FPGAs which provide a 'gated clock' but they do the gating at
the row or region driver level, as that is where you get better power
savings (driving the clock tree is a significant use of power, while
gating at the flip-flop level saves virtually nothing, if it doesn't
cost you due to the extra logic, if it needs a LUT to gate, you have lost)

These gated clock drivers tend to have de-glitching logic on them that
makes them safe to use (gate signal low keeps the output clock from
going high but doesn't force a high output low). This says that you can
save power if you know a whole section won't be changing for awhile, but
unlikely helps on a small state machine that occasionally doesn't
change, as the power in the change prediction logic may cost more than
the savings. Also, since these clock drivers are a limited critical
resource, you likely don't have enough to use it fine grain.

Who makes these FPGAs? Are these in the typical clock generators most FPGAs have only a handful of? That's still better than no clock gating.

Microsemi, now part of Microchip. The gating is part of the regional
clock driving tree, so is somewhat limited, but not as limited as the
master clock generators (which also have gating).

Which products. I was just looking at their site the other day and I didn't see anything remotely new. Maybe I missed this? Or is this not new?

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

KJ
Guest

Sun Dec 01, 2019 12:43 am

On Friday, November 29, 2019 at 10:56:36 PM UTC-5, Weng Tianxiang wrote:

Quote:
1. It became patent US 10482208 since 11/19/2019.

OK, you paid your filing fee and convinced a bureaucrat so why are you going on about it in comp.arch.fpga?

Quote:
2. If you can pinpoint any unsubstantiated claim from the official US patent, what you make may invalidate the patent.

Why would I care to let you know about that?

Quote:
3. I welcome your action and have no objection against it, because I believe the state machine's new coding method certainly will be accepted into HDL SOMEDAY, because it generates no burden for coding state machines and finally perfects the work made by a lot of papers one of which has 224 cites,
http://www.scarpaz.com/2100-papers/Low%20Power/00503933.pdf,
and every code designer will benefit on the new coding method.

As I pointed out to you before, because you've chosen to patent, it essentially cannot be accepted into an HDL standard, regardless of the merit.

Quote:

KJ, please be BRAVE to pinpoint WHICH PAGE, WHICH LINES 哦人WHICH FIGURES have any type of LOGIC and SIGNIFICANT errors.

HAHAHAHA, that would be a paid position, not one that should be done for free. Good try. Just like the one you did earlier in this thread where you encouraged others to be unethical to their own employers in regards to offering a bounty for infringing your patent. Asking others to be unethical is itself unethical, but I don't think you see it that way.

Quote:
If you do this I will response to your points immediately and let Rick and HT-Lab determine if your claim is pointless or not, otherwise I will ignore all your later posts on this subject.
You don't respond to any points...you reply, but no response. That's why we have these pointless back and forths, I point out your flaws or challenge you to backup your claim with real data and you never come through.

Quote:

9 (nine) years ago I asked you to help me to check the application text for grammar errors and I thank you for your help with paying.

Grammar errors, right...OooooKkkkk. I provided valid technical feedback because nearly everything you claimed at that time was wrong and I demonstrated it to you with actual designs and reports. Grammar errors...I did do some of that too, but wow.

Quote:
Now it became a patent with all brand new figures and specifications you have never seen it before publication, and all figures, specification, claims for the patent were made by myself.
I've only been commenting on what you've posted here in this forum. You just can't seem to follow...again

Kevin Jennings

Goto page Previous  1, 2, 3  Next

elektroda.net NewsGroups Forum Index - FPGA - New coding method for a state machine in groups in HDL