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Swapnil Patil

Tue Sep 18, 2018 12:45 pm   

Hello folks,

I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state machine.

The problem with simulation result is that it is writing data properly but not reading it.I do not understand what is problem?

here is my testbench Data in sent internally via array.

ENTITY mainfiletb12 IS
END mainfiletb12;

ARCHITECTURE behavior OF mainfiletb12 IS

-- Component Declaration for the Unit Under Test (UUT)

CLK_10_MHz : IN std_logic;
ResetN : IN std_logic;
SCL1 : OUT std_logic; --serial clock input
SDA1 : INOUT std_logic; ---serial data
Read_WriteN : IN std_logic;---read write bit 1 for read, 0 for write
AddressIn : IN std_logic_vector(7 downto 0); --Register address
Ack1 : OUT std_logic; --acknoledge bit
DataOut1 : OUT std_logic_vector(7 downto 0); --output data

StateOute : OUT std_logic_vector(7 downto 0); -- state register
RegisterAddressOut1 : OUT std_logic_vector(7 downto 0)

signal CLK_10_MHz : std_logic := '0';
signal ResetN : std_logic := '0';
signal Read_WriteN : std_logic := '0';
signal AddressIn : std_logic_vector(7 downto 0) := (others => '0');

signal SDA1 : std_logic;

signal SCL1 : std_logic;
signal Ack1 : std_logic;
signal DataOut1 : std_logic_vector(7 downto 0);
signal StateOute : std_logic_vector(7 downto 0);
signal RegisterAddressOut1 : std_logic_vector(7 downto 0);

-- Clock period definitions
constant CLK_10_MHz_period : time := 100 ns;


-- Instantiate the Unit Under Test (UUT)
uut: Main_file PORT MAP (
CLK_10_MHz => CLK_10_MHz,
ResetN => ResetN,
SCL1 => SCL1,
SDA1 => SDA1,
Read_WriteN => Read_WriteN,
AddressIn => AddressIn,
Ack1 => Ack1,
DataOut1 => DataOut1,
Dataw => Dataw,
StateOute => StateOute,
StateOut3 => StateOut3,
RegisterAddressOut1 => RegisterAddressOut1

-- Clock process definitions
CLK_10_MHz_process :process
CLK_10_MHz <= '0';
wait for CLK_10_MHz_period/2;
CLK_10_MHz <= '1';
wait for CLK_10_MHz_period/2;
end process;

-- Stimulus process
stim_proc: process
-- hold reset state for 100 ns.
wait for 100 ns;

wait for CLK_10_MHz_period*10;

-- insert stimulus here
----intial reset condition----
ResetN <= '0';
wait for 50 ns;
ResetN <= '1';
wait for 100 ns;

---Address register ---
AddressIn <= x"02";

end process;


Tobias Baumann

Thu Sep 20, 2018 1:45 am   


can you please explain a bit more detailed what the problem is? What
signals are showing unexpected behavior and which behavior do you expect?

The component main_file is currently a black box, I should also provide
the source code of this component.

Viele Grüße,


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