Need an algorithm for BIST to test stuck at faults in an FPG

Tue Apr 25, 2006 2:20 am   

Hi,

I need an algorithm or verilog/vhdl code for Built in self test that
can detect stuck at faults in an FPGA. Please help me in this case

Thanks,
Pavan

Thu Apr 27, 2006 4:04 pm   

"pavan.bvsrc_at_gmail.com" <pavan.bvsrc_at_gmail.com> writes:


Why? FPGAs are already tested when you get them.

You could ask on comp.arch.fpga, but they'll say much the same I
imagine :-)

Cheers,
Martin

--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

Sat Apr 29, 2006 6:51 pm   

FPGAs offer JTAG and boundary scan which you can use to access
internals for design verification purposes (testing the design).
Manufacturing testing of FPGAs (like stuck-at testing) is already
performed on FPGAs when you buy them.

Maybe you need to implement a BIST variant in an FPGA just to
explore/practice, then google LFSR BIST VERILOG.

Good Luck.

HrH