need a cheap student edition FPGA

I would recommend you to start reading the book by Samir Palnitkar.
That is the best I have seen for beginners.

-Anil


yupeng__at_hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0306281807.14b6400f_at_posting.google.com>...
Hi,
I'm studying verilog and Synopsys DC. There are a lot of materials
on the WEB. Could somebody introduce the best materials to a beginner?
Best wishes,
Peng

Hi,
I'm studying verilog and Synopsys DC. There are a lot of materials
on the WEB. Could somebody introduce the best materials to a beginner?
Best wishes,
Peng

ben cohen wrote:

And in some cases, it is better that the verification team be an
automonous entity. I've done a bunch of reasearch on verification,
and there's good things about 'pure' verification environments. (And
frankly, most designers write terrible test benches! I'm sure Ben
will back me up on this one. :)


(I think I lost some attribution somewhere)

It would seem that autonomy is an almost necessary condition for
verification. All of my verification work has been done on (what was
intended to be) production silicon/boards; with nothing to guide me but
a product spec document. My job was, of course, to determine if the
implementation behavior matched the spec; and to communicate mismatching
behaviors to the client. Once a problem was detected I met with members
of the design team to discuss the problem. Sometimes it was a matter of
intending one thing but saying another in the spec, sometimes a
misunderstanding of the spec on my part, and sometimes it was a genuine
bug.

The designers seemed to be afflicted with an automatic denial response
("No bugs in /my/ design!") I can confirm that people with real genius
for logic design frequently display a real lack of talent for writing
test code - especially test code that really stresses their design. I
just love being told that my test programs are /too/ fast for the
hardware :-)

On the other hand, I've been fortunate in working with designers who
were unbelievably cooperative and helpful. These qualities are major
cost reducers and time savers in the verification process.

Note that my niche has not been in hardware design; but is rather in
testing embedded [whatever]. If you'd like a glimpse into my most recent
such project, there's a thumbnail sketch at:
http://www/iedu.com/mrd/philips.txt

Hi to all,

someone could suggest me a PC tool able to do an Analog-Digital simulation?
Let me say a mixed HDL-PSpice sim?

Thanks

Riccardo

You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think). It translates State Machines, Flow Diagrams, FSM into
Verilog, vhdl and SystemC. All ready for synthesys.

I pesonnally think that hardware desining can be outsourced (with
correct spec). Once designed there is a lot of responsibility on people
to ensure that the designed hardwrea meets the specification.

any commnts most welcomed.

Well, the key is communication. It is sometimes difficult to get a consensus

You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think).
Hmmm, Mentor, who created Renoir (now HDL Designer). I suspect one of

The FSM below has been waking-up in an illegal state and I can't figure out
why. This is in actual hardware (XC2V1000). I must be missing something
fundamental.

parameter RESET = 3'b001;
parameter CTL_HIGH = 3'b010;
parameter GO = 3'b100;

reg [2:0] input_state = RESET;

always @ (posedge CLK_IN) begin
if(RST_IN) begin
input_state <= RESET;
end
else
case (input_state) //synthesis parallel_case full_case
RESET: begin // Monitoring for control signal to go high
FIFO_WRITE_ENABLE <= 1'b0;
if(CONTROL_IN) input_state <= CTL_HIGH;
end

CTL_HIGH: begin // Now wait for it to go low
if(!CONTROL_IN) begin
FIFO_WRITE_ENABLE <= 1'b1;
input_state <= GO;
end
end

GO: begin // Stay here unless reset
FIFO_WRITE_ENABLE <= 1'b1;
input_state <= GO;
end
endcase
end

The FSM simply waits for a pulse to go high and then low again before
permanently enabling an external (to the module) FIFO to go. I know there
are other ways to do this ... but humor me here, I'm trying to figure out
why this is broken.

I use upper case variable names to denote module I/O. Lower case variables
are internal to a module.

For debugging purposes I brought out "input_state" to three pins on the
device. A scope clearly shows that sometimes this FSM will wake-up with
input_state = 3'b000. Can anyone tell me how this is possible? The problem
is particularly frustrating because it comes and goes as work is done in
other modules. Maybe some sort of placement/timing issue? The clock is
about 100MHz.

Thanks,

I need to model a bus in my system as a "trireg" or "wire" depending
on the test that is running.

The trireg bus models a capacitive bus that holds its previous value
when not driven.

My current solution is to use a `define to choose the type of bus:

`ifdef USE_TRIREG_BUS
trireg [15:0] my_bus;
`else
wire [15:0] my_bus;
`endif

Unfortunately, this solution requires me to compile multiple versions
of the simulator (using VCS7.0). I need to choose a trireg or wire
bus at runtime. The type of bus will not change during the
simulation. I would like to compile one simlator and pass a plusarg
(like +use_trireg_bus) instead of a `define to determine the type of
bus to use.

This is the best that I could come up with. Unfortunately, this
solution generates bus contflicts on my_bus.

reg use_trireg_bus;

initial begin
if ($test$plusargs("use_trireg_bus"))
use_trireg_bus = 1;
else
use_trireg_bus = 0;
end

wire [15:0] my_bus;
trireg [15:0] my_bus_stub;
tranif1 my_bus_trans[15:0] (my_bus_stub[15:0], my_bus[15:0],
use_trireg_bus);

Does anyone know how to implement this properly in Verilog?

- Dale

Hi,
Are UDP and case statement same for some combinational logic? What's
the difference between the following two implementation of MUX? Under
what condition should we use UDP? Under what condition should we use
case statement?
Peng

primitive prim_mux4to1 (DOUT, DIN3, DIN2, DIN1, DIN0, SEL1, SEL0);
output DOUT;
input DIN3, DIN2, DIN1, DIN0, SEL1, SEL0;

table
???0 00 : 0;
???1 00 : 1;
??0? 01 : 0;
??1? 01 : 1;
?0?? 10 : 0;
?1?? 10 : 1;
0??? 11 : 0;
1??? 11 : 1;
endtable
endprimitive

module mux16to1 (DIN, SEL, DOUT);
input [15:0] DIN;
input [3:0] SEL;
output DOUT;
reg DOUT;

always@(SEL or DIN)
begin: blk1
case (SEL) // synopsys infer_mux
4'b0000: DOUT <= DIN[0];
4'b0001: DOUT <= DIN[1];
4'b0010: DOUT <= DIN[2];
4'b0011: DOUT <= DIN[3];
4'b0100: DOUT <= DIN[4];
4'b0101: DOUT <= DIN[5];
4'b0110: DOUT <= DIN[6];
4'b0111: DOUT <= DIN[7];
4'b1000: DOUT <= DIN[8];
4'b1001: DOUT <= DIN[9];
4'b1010: DOUT <= DIN[10];
4'b1011: DOUT <= DIN[11];
4'b1100: DOUT <= DIN[12];
4'b1101: DOUT <= DIN[13];
4'b1110: DOUT <= DIN[14];
4'b1111: DOUT <= DIN[15];
endcase
end
endmodule

Dear people,

I create a module, for example, a simple adder in Verilog. It synthesises
fine. I then create a schematic symbol from it, but the ".sym" file
contains
very little information, and when I place it in to a schematic module in
the
project, no symbol appears.

Has anybody else had the same problem? I am using the latest ISE (5.2 with
SP 3) as part of the WebPack.

Regards to all

PETE MASH

"Peter Mash" <pwtm2_at_cam.ac.uk> wrote in message
news:<bf3up7$4a2$1_at_pegasus.csx.cam.ac.uk>...
Answer found:

It's because the schematic symbol generator doesn't support Verilog 2001

Out of curiosity, what Verilog-2001 feature were you using?

Since you said it was a simple module, I am guessing ANSI-C-style
module declarations.

Hi,

I am looking for SystemC IP cores for some video/SoC applications
(like MPEG4, mp3 decoder, etc.).

Is it possible to get such SystemC cores for free from somewhere?

thanks

-srini

Hi to all,

someone could suggest me a PC tool able to do an Analog-Digital simulation?
Let me say a mixed HDL-PSpice sim?

Thanks

Riccardo

Hello,
I would like to download the IEEE 1364.1 LRM that deals with the
synthesizable subset of
verilog. Can anyone in the group provide me with pointers from where i
can get this done?
Also any documents pertaining to the internals of the sis package from
berkeley would be of
great help. Thanks in advance for any help.