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Sajan
Guest
Wed Sep 29, 2004 7:49 pm
All this cringe and moan about job losses.
How narrower can a human mind get.
When are we going to understand that whoever gets the job
ahead of you perhaps deserves it more , may be cause hes more skilled,
or may be cause hes cheaper, but for sure he deserves the job
much more than you.
The narrower the mind gets. Will u guys come out in the open and
say jobs only for those born on and brought up in silicon valley ,
the other US people are outsiders. No jobs to people from Texas and Virginia,
cause we dont have enough jobs in California?????
So why this cringe and moan when the job goes to an Indian,
hes also a fellow human being mate, just like any fellow american.
Marco Fioretti <Marco.Fioretti_at_ericsson.com> wrote in message news:<401A5DA1.3B31E21C_at_ericsson.com>...
Quote:
Abhijit wrote:
I have been reading all the messages and I would like to add my 2
paisa (since I live in India) worth to this discussion.
I am sorry if I hurt anyone's feelings here...
I'm almost sure you didn't hurt the feelings of anybody with
common sense and the courage to be objective.
Very good summary of the problem and its causes. Well said.
Ciao,
Marco
Tom Joad
Guest
Wed Sep 29, 2004 7:49 pm
"fabbl" <yttt_at_nukes.com> wrote in message news:<vxgSb.1995$9f6.1596_at_newssvr31.news.prodigy.com>...
Quote:
I agree. Kids in the US are interested in being MBA's , lawyers and pop
stars.
At this point if you met an American highschool student that might be
inclined toward going into engineering, would you recommend it to
them? I certainly wouldn't. I would recommend that they get into a
field that cannot be outsourced if they want stability. If they don't
care about stability, they may was well get an art degree as get an
engineering degree.
Quote:
There is definitely no glamour being an engineer. Nor is it going to
make you rich.
Perhaps not, but it used to provide a very solid living. And some of
it was very interesting, creative and intellectually stimulating work.
Quote:
Many masters and Ph.d. programs are filled with asian students. Your lucky
to see one or two Americans in any advanced technology degree programs.
I've been one of those. Was it worthwhile getting a Masters degree?
At this point it seems like it was a huge waste of time and $$$. Even
prior to the downturn it seemed like a waste primarily because
academia was so far behind industry. I came to the conclusion that in
this field you learn a lot more by working in it than by getting an
advanced degree. Most of the professors had no idea what was going on
in industry. They tended to have quaint notions about what industry
must need. I was very disappointed with the whole graduate degree
thing; I thought it was supposed to be about pushing the envelope and
researching new ideas, but it wasn't that way at all. I really can't
see why someone with a new Masters degree would be more desirable to a
company than an engineer with a Bachelors degree who had been working
in the field for a long time, and yet you would see it all the time
back when jobs were posted "Masters degree required". So I decided to
get one just to jump through the hoops. But that's a different
topic...
Quote:
The
whole overseas/foreign out-source phenomena is due in large part to talent
shortages. I say the market will correct itself in time, but the India as a
major source of technical talent is here to stay.
Granted, three or four years ago during the boom there was a talent
shortage in the US and we did need to import workers. Now there is a
talent surplus. If things get better again, how exactly are we
supposed to address the so-called talent shortage? Are we supposed to
go into the highschools and encourage more students to become
engineers when they see that lots of engineers were recently
unemployed? It's not going to give them a lot of confidence that
they'll find work after they graduate.
Tom Joad
fabbl
Guest
Wed Sep 29, 2004 7:49 pm
I'm not cringing or whining one bit. The US made their bed and now will lay
in it. It is too expensive and their are too many alternatives to doing
engineering in the US. Why should companies cower to people who can't face
facts? If I can hire an Indian or Asian engineer who has a 3.9 GPA, willing
to work hard for $20,000 bucks/year than why not? These flag-waving idiots
crying about lost jobs sure as hell want a good deal when they go shopping -
and the only reason they would get a good deal is because some business man
got one too.
Competition is good.
Rob Dekker
Guest
Wed Sep 29, 2004 7:49 pm
Hi Wando,
We (Verific) provide a Verilog-AMS parser, which is free in evaluation form
(a binary that reads AMS, and elaborates and writes out elaborated tree).
But you cannot do much with it unless you want to license the (C++) sources
and build your own EDA tool with it.
What do you want to do after you parse ?
Rob
"wanbo" <wanbo_at_u.washington.edu> wrote in message
news:bd84ik$28g6$1_at_nntp6.u.washington.edu...
Quote:
Hi,
Anybody knows if there is a free Verilog-A parser? I do check the faq, but
there is only info about Verilog parser...
Thanks,
Bo
oiwo
Guest
Wed Sep 29, 2004 7:49 pm
Quote:
"don" <don_at_nowhere.net> wrote in message
news:gN%Ia.558$x7.59613245_at_newssvr21.news.prodigy.com...
warning, whining complaint follows...
My company is starting a new ASIC project where I'd like
to use Verilog-2001 (instead of Verilog-1995.) I bought
Palitknar's Verilog-HDL 2nd edition (ISBN 0130449113)
which covers the IEEE 1364-2001 Verilog.
I'd like to dissuade others from buying Palnitkar's book. I checked out
the
new edition briefly and it appeared that the originally inadequate book
had
been barely modified for the 2nd edition, with the exception that the
cover
now states that it covers Verilog-2001. The new file i/o commands are
covered by a footnote that only acknowledges their existence. I'm not
even
sure the book was reprinted. Wait for something better.
I must admit, the 2nd edition adds very little to the first edition.
But I still consider Palitknar's an excellent *starter* (tutorial) book. I
found the discussion of major topics (RTL, gate, behavioral) easy to follow
and the examples really help. After reading this book, I felt ready to
tackle more advanced (and practical) books which require Verilog background.
Marcin
Guest
Wed Sep 29, 2004 7:49 pm
dew814_at_aol.com (Dave Ardrey) wrote in message news:<20de6cd6.0306201125.15ed413c_at_posting.google.com>...
Quote:
I'm trying to set a path delay in my verilog module like so:
(posedge CLK => Q[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
However, when I try to simulate with VerilogXL I get the following
error:
Error! Outputs for edge-sensitive paths have to be
associated with data source
[Verilog-OESDS]
"RA1SD.new", 544: (posedge CLK=>Q[15]) = 1, 1,
0.5, 1, 0.5, 1;
1 error
Quote:
I've seen a line exactly like the one I have in the VerilogXL
reference guide. Any ideas what's going on here?
Thanks!
Hello Dave,
You have to choose.
simple path...
(CLK => Q[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
or edge-sensitive path :
(posedge CLK => (Q[15] +: I))=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
where I is your input.
VerilogXL expected the second one.
Marcin
y_p_w
Guest
Wed Sep 29, 2004 7:49 pm
rickman <spamgoeshere4_at_yahoo.com> wrote in message news:<3EF7744D.1CF9F6D_at_yahoo.com>...
Quote:
Tauno Voipio wrote:
"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3EF744FB.AF2FB36E_at_yahoo.com...
Tauno Voipio wrote:
"y_p_w" <y_p_w_at_hotmail.com> wrote in message
news:591da479.0306230937.42883d68_at_posting.google.com...
Hi-
I'm currently in the process of creating a synthesizable Verilog
F/S I2C slave, but have little experience with I2C in the real
world.
I'm reading the specs, and I feel I'm getting a pretty good
understanding. If I'm getting this right, the SDA line will only
change when the SCL line is low - except when the master is
indicating a START or STOP command.
So the question I have for those who have really done this is -
in the real world, could a master (or series of masters) issue
a STOP command followed by a START command - all on the same
SCL high period. The latest I2C spec doesn't explain whether
or not this could happen.
This is key to me, since I'm trying to create an I2C slave that
runs solely off the SDA and SCL signals. Whether or not I have
to deal with START and STOP on the same SCL high period will
impact the design choice I make.
AFAIK, that's normal when the bus is idle in the meantime.
The idle bus has all drivers loose and both lines up. When the master
ends a
transmission, the last thing is the STOP condition: SCL up, then SDA up.
When the next transmission starts, the first thing is the START
condition:
SCL still up, SDA down.
I think he means the other way around, a START followed by a STOP with
no clock transitions inbetween. In essence, this would be an "empty"
frame.
I have not worked with I2C before, so I don't know the answer. But I am
interested since I will be making one as well.
I have not checked opencores.org, but it seems likely that they would
have a core for this. It might be a bit larger than you would want to
use however.
An empty frame is expressely forbidden in the specs. However, the logic must
still not hang up if such a condition should happen.
Tauno Voipio
tauno voipio @ iki fi
I guess that is the answer then. The condition should not occur, but if
it does due to a defect in one component, it should not cause a problem
in another component.
To the OP,
How does this change your design? I would think an empty frame would be
handled like one that is not addressed to your device, no?
Well - here's my concerns and thinking:
1) It seems that the preferred method is to have a STOP condition
(SDA rising when SCL=1) on the same SCL high period as a START
period (SDA falling when SCL=1). This would look like this:
_________________________
SCL ___| |_____
_________________
SDA _______| |_________
2) As far as I can tell the spec says nothing about SCL changing
between a STOP and START. I wouldn't see any advantage to it,
but I couldn't sense it was illegal. I would suppose any
clock toggling before a START should just be ignored until a
START is detected.
3) I was worried about whether a master could "change its mind"
after issuing a start if it was suddenly occupied with something
considered more important. Fortunately, this doesn't seem to
be a problem.
4) Most of what I'm planning is a straightforward FSM clocked on
the negedge of SCL. The START and STOP logic I'm planning on
using isn't as straightforward. This was the part that would
have been messed up if I had to account for multiple START or
STOP methods. I wanted to create a START detected signal, and
use that to tell the FSM when to start monitoring SDA.
5) I could possibly use a high-speed internal clock. However -
the goal is a low-power design, and I was told that just
toggling the clock tree would create unnecessary power
consumption.
y_p_w
Guest
Wed Sep 29, 2004 7:49 pm
rickman <spamgoeshere4_at_yahoo.com> wrote in message news:<3EF86106.BCB1DCB_at_yahoo.com>...
Quote:
y_p_w wrote:
Well - here's my concerns and thinking:
1) It seems that the preferred method is to have a STOP condition
(SDA rising when SCL=1) on the same SCL high period as a START
period (SDA falling when SCL=1). This would look like this:
_________________________
SCL ___| |_____
_________________
SDA _______| |_________
2) As far as I can tell the spec says nothing about SCL changing
between a STOP and START. I wouldn't see any advantage to it,
but I couldn't sense it was illegal. I would suppose any
clock toggling before a START should just be ignored until a
START is detected.
3) I was worried about whether a master could "change its mind"
after issuing a start if it was suddenly occupied with something
considered more important. Fortunately, this doesn't seem to
be a problem.
4) Most of what I'm planning is a straightforward FSM clocked on
the negedge of SCL. The START and STOP logic I'm planning on
using isn't as straightforward. This was the part that would
have been messed up if I had to account for multiple START or
STOP methods. I wanted to create a START detected signal, and
use that to tell the FSM when to start monitoring SDA.
5) I could possibly use a high-speed internal clock. However -
the goal is a low-power design, and I was told that just
toggling the clock tree would create unnecessary power
consumption.
I have not given this a lot of thought, but I believe you can use two
FFs (with resets) to detect the start/stop conditions and maintain a
state of disabled/enabled.
The start FF is clocked on the falling edge of SDA with SCL on the D
input. This FF will be set on a start condition. The stop FF will be
clocked on the rising edge of SDA with SCL on the D input. This FF will
be set on the stop condition. The start FF being off will hold the stop
FF in reset. The stop FF being set will reset the start FF. So the
sequence will be;
1) both FFs clear
2) on start, the start FF is set and the rest of the circuit is enabled
3) on stop, the stop FF is set which clears the start FF
4) the start FF being cleared also clears the stop FF
I had something a little different, but not far off from your suggestion.
Think masking off one signal with the other.
Quote:
The only issue I can see with this design is that the stop FF will
generate a reset pulse determined by the time it takes to reset both FFs
plus the routing. Some people would object to this saying it may
violate the timing requirements of your logic. If so, you may want to
use the LUT or the OR array with the FF to add some extra delay. In
general this should work ok since it is basically self timed logic.
On the other hand, using a synchronous design should not consume much
power. Unless you are going for power below 100 uA, a low power CPLD
(like the coolrunner) should be able to run at 1 MHz (fast enough for
most I2C chips at 400 kb/s) with power at that level.
I won't go into the proprietary details, but I'm doing this work for an
SoC design that might be battery powered in some applications. My boss
is keen on reducing power consumption during a standby mode.
I also apologize if I don't get into specifics about my planned design
that might explain my problems. As with many in these NG's, I work at
a large company that considers the product I produce confidential. If
this works well, I (personally) wouldn't be averse to submitting this
as an open source Verilog block. However - I'd have to make sure this
is OK with my employer.
Yu-Ping Wang
Berkeley, California
Uwe Bonnes
Guest
Wed Sep 29, 2004 7:49 pm
srinivas turaga <srinivas_turaga_at_indiatimes.com> wrote:
: Hi all,
: can any tell what could be its equivalent in verilog.
: i want to know what is exact verilog equivalent to weak high 'H' in vhdl.
: entity pullup is
: port (.........
: ..........
: x: out std_logic
: ............
: ...............
: begin
: ...........
: if y ='1' then
: x<='1'
: else
: x<='z';
: end if
: ...........................
: ........................
Try
wire x;
pullup(x);
or
tri1 x;
Hope this helps
--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Asher C. Martin
Guest
Wed Sep 29, 2004 7:49 pm
cuteworm_at_wildmail.com (walter) wrote in message news:<36659e9e.0306180744.1756095_at_posting.google.com>...
Quote:
Hi,
Is there is any Verilog model for PLL?
I tried the google search.
But they are not really related to what I need.
Hi,
Altera has a FREE PLL model available when you install the Quaruts II
Web Edition Software.
https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp?xy=qw1_wdl
Go to the /quartus/eda/sim_lib/ dir and type "grep pll *.v"
Take care,
>Asher<
Jonathan Bromley
Guest
Wed Sep 29, 2004 7:49 pm
On Thu, 26 Jun 2003 16:53:12 -0700, Tze Yi Yeoh
<tzeyi.yeoh_at_xilinx.com> wrote:
Quote:
Does anyone out there know if Verilog supports operator overloading like
in VHDL? If so, can someone point me to an example?
No, it doesn't.
SystemVerilog 3.1 will offer classes, but AFAIK still no operator
overloading.
Jonathan Bromley
Ashraf
Guest
Wed Sep 29, 2004 7:49 pm
asherm_at_asherm.com (Asher C. Martin) wrote in message news:<3e30b793.0306260956.206290ef_at_posting.google.com>...
Quote:
There is an article which highlights the approach when I developed this model
while I was working for a Silicon vendor. I can't share you all the details
(company proprietary information), but you can pick up the idea from the
IEEE CICC proceedings 1997 Page 15.6.1-15.6.4.
This is full functional PLL model which mimics the functionality of Lockup
sequence, frequency synthesis and selection of loop filter parameters and their
affect on lock time etc etc.
Good Luck,
Ashraf
> >Asher<
DSLuser
Guest
Wed Sep 29, 2004 7:49 pm
WJ wrote:
Quote:
I am tring to do back-annotation by Verilog, and encounter a problem
as following:
since the instance name is too long, up to 25 characters for a single
instance name, PrimeTime generated the sdf base on the those long
instance names, but looks Verilog-XL can take only up to 24 charaters
as instance names, the last charater is automatically truncted in this
case. I dumped the waveform to confirm this Verilog-XL instance name
trunction, and also double confirm this problem by modify the sdf
file.
Anybody know how to solve this problem? Is there any option in
Verilog-XL for taking long instance name? Thanks in advance!
I think Verilog-XL is nearing 'end-of-life' development status.
Although Cadence officially still provides support for the Verilog-XL
product, I don't think they are not updating it anymore. For example,
Verilog-XL supports very few IEEE 1364 Verilog-2001 syntax.
Since you can't change Verilog-XL's behavior, you have two choices:
1) use a different verilog simulator (Cadence NC-verilog,
Mentor Modeltech VSIM, Synopsys VCS are all good choices)
2) modify your netlist (like you did), to limit the length
of instance names. If you're really good with PERL, you
could handwrite a script to do something like this.
Finally, why are your instance names so long? Are you using
parameterized instances? If so, you may want to give your
RTL-synthesis 'hints' before elaboration. I think there is a
way to do this in Synopsys Design Compiler (if that's what you're
using.) You tell Design Compiler specific instances to build
(you tell it to build different versions of the parameterized
instance...you manually specify the parameter values.) Then,
when the parameterized instances are later used in other
modules, Design_Compiler automatically looks in its 'library',
and pulls your hand-specified version. I think this will
shorten the instance names, but I never tried it.
Ajeetha Kumari
Guest
Wed Sep 29, 2004 7:49 pm
Hi tze,
NO, as such Verilog doesn't have user defined data types and hence
I guess this was not thought about either. Can you elaborate more on
which scenario would you need this? Perhaps there is an alternate
solution (I remember reading something similar in Deepchip.com's
archive, but related to $finish and specific to VCS).
HTH,
Aji
http://www.noveldv.com
Tze Yi Yeoh <tzeyi.yeoh_at_xilinx.com> wrote in message news:<3EFB8768.B636CD0D_at_xilinx.com>...
Quote:
Does anyone out there know if Verilog supports operator overloading like
in VHDL? If so, can someone point me to an example?
thanks!
tze
Anil Dalwani
Guest
Wed Sep 29, 2004 7:49 pm
I would recommend you to start reading the book by Samir Palnitkar.
That is the best I have seen for beginners.
-Anil
yupeng__at_hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0306281807.14b6400f_at_posting.google.com>...
Quote:
Hi,
I'm studying verilog and Synopsys DC. There are a lot of materials
on the WEB. Could somebody introduce the best materials to a beginner?
Best wishes,
Peng
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