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Prasanna
Guest
Guest
Wed Sep 29, 2004 7:49 pm
"hrwieuyriwru" <jkshdfkjhskdjfksfksd_at_dfuosdf.com> wrote in message news:<WyHVa.696$il2.75461696_at_newssvr21.news.prodigy.com>...
Quote:
"Subroto Datta" <sdatta_at_altera.com> wrote in message
news:qXuUa.3036$NV3.1143_at_newssvr31.news.prodigy.com...
Multicycle paths are paths between registers that intentionally take more
than one clock cycle to become stable. For example a register may need to
trigger a signal every second or third rising clock edge.
A False path is any path that is not relevant to a circuit's operation.
A good description of both multicycle and false paths can be found in the
following Timing Analysis App Note:
http://www.altera.com/literature/an/an123.pdf
Subroto Datta
Altera Corp.
From a conceptual standpoint, these definitions are mostly correct.
But be aware that different CAD-tool vendors (Synopsys, Cadence,
etc.) may treat the *operational* meanings of false-path differently..
In Synopsys's case, their application manuals have clear
examples when to use 'set_disable_timing' versus 'set_false_path.'
The problem with set_false_path is that it can (unintentionally)
affect more than just timing-constraints.
"LIJO" <lijo_eceNOSPAM_at_hotmail.com> wrote in message
news:bftlvd$iao78$1_at_ID-159866.news.uni-berlin.de...
Hi,
Can anyone tell me what is Multi Cycle path and False path?
thanks
Lijo
news:qXuUa.3036$NV3.1143_at_newssvr31.news.prodigy.com...
Multicycle paths are paths between registers that intentionally take more
than one clock cycle to become stable. For example a register may need to
trigger a signal every second or third rising clock edge.
A False path is any path that is not relevant to a circuit's operation.
A good description of both multicycle and false paths can be found in the
following Timing Analysis App Note:
http://www.altera.com/literature/an/an123.pdf
Subroto Datta
Altera Corp.
From a conceptual standpoint, these definitions are mostly correct.
But be aware that different CAD-tool vendors (Synopsys, Cadence,
etc.) may treat the *operational* meanings of false-path differently..
In Synopsys's case, their application manuals have clear
examples when to use 'set_disable_timing' versus 'set_false_path.'
The problem with set_false_path is that it can (unintentionally)
affect more than just timing-constraints.
"LIJO" <lijo_eceNOSPAM_at_hotmail.com> wrote in message
news:bftlvd$iao78$1_at_ID-159866.news.uni-berlin.de...
Hi,
Can anyone tell me what is Multi Cycle path and False path?
thanks
Lijo
Here are some examples I can think of.
Lets say you have a mode bit that you use in your logic and you know
some paths specifically do not exist when the core is not in that
mode, that becomes a false path.
Lets say, you do a complex logic such as a CRC and find that your
final CRC evaluation takes more than one clock cycle (based on byte
enables) and cannot meet the speed requirements. You can pipeline the
data and calculate final CRC in multiple clock cycles.
Open to learn more
rickman
Guest
Guest
Wed Sep 29, 2004 7:49 pm
Prasanna wrote:
Quote:
Here are some examples I can think of.
Lets say you have a mode bit that you use in your logic and you know
some paths specifically do not exist when the core is not in that
mode, that becomes a false path.
Lets say, you do a complex logic such as a CRC and find that your
final CRC evaluation takes more than one clock cycle (based on byte
enables) and cannot meet the speed requirements. You can pipeline the
data and calculate final CRC in multiple clock cycles.
This is exactly what multicycle is not. If you allowed the CRC
calculation to have two or three clock cycles for the logic delays to
settle out and used an enable on the register at the end, that would be
a multicycle path. This requires a separate multicycle timing spec
since otherwise the tool will try to optimize this to get it to run in
one clock cycle. If you add pipeline registers, then each stage will
need to be done in a single clock cycle and will definitely *not* be
multicycle.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Prasanna
Guest
Guest
Wed Sep 29, 2004 7:49 pm
rickman <spamgoeshere4_at_yahoo.com> wrote in message news:<3F2923F5.32975097_at_yahoo.com>...
Quote:
Prasanna wrote:
Here are some examples I can think of.
Lets say you have a mode bit that you use in your logic and you know
some paths specifically do not exist when the core is not in that
mode, that becomes a false path.
Lets say, you do a complex logic such as a CRC and find that your
final CRC evaluation takes more than one clock cycle (based on byte
enables) and cannot meet the speed requirements. You can pipeline the
data and calculate final CRC in multiple clock cycles.
This is exactly what multicycle is not. If you allowed the CRC
calculation to have two or three clock cycles for the logic delays to
settle out and used an enable on the register at the end, that would be
a multicycle path. This requires a separate multicycle timing spec
since otherwise the tool will try to optimize this to get it to run in
one clock cycle. If you add pipeline registers, then each stage will
need to be done in a single clock cycle and will definitely *not* be
multicycle.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Here are some examples I can think of.
Lets say you have a mode bit that you use in your logic and you know
some paths specifically do not exist when the core is not in that
mode, that becomes a false path.
Lets say, you do a complex logic such as a CRC and find that your
final CRC evaluation takes more than one clock cycle (based on byte
enables) and cannot meet the speed requirements. You can pipeline the
data and calculate final CRC in multiple clock cycles.
This is exactly what multicycle is not. If you allowed the CRC
calculation to have two or three clock cycles for the logic delays to
settle out and used an enable on the register at the end, that would be
a multicycle path. This requires a separate multicycle timing spec
since otherwise the tool will try to optimize this to get it to run in
one clock cycle. If you add pipeline registers, then each stage will
need to be done in a single clock cycle and will definitely *not* be
multicycle.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
I guess you know what I meant on multicycle path on calculating final
CRC. I was not mainly addressing the issue how to use pipeline here. I
used the word pipeline there to address the issue of what do you do
with the incoming data when the logic is taking multiple clock cycles
to complete a job. I think designers do understand how to keep data
stable for more clocks with enables.
Guess I focussed my point this time on multicycle path.
Nicholas C. Weaver
Guest
Guest
Wed Sep 29, 2004 7:49 pm
In article <3F2A868E.85807215_at_yahoo.com>,
rickman <spamgoeshere4_at_yahoo.com> wrote:
Quote:
Not always true. Anytime you add a register, you have to add setup time
and output delay to your path. Plus your path must be broken
arbitrarily and it is not simple to pick the optimal points. By not
adding registers and using an enable on the one register, you allow the
full N clock cycles for the logic to settle. This was exactly how we
designed an ATM chip. Once the cell had been received we had three
clocks to analyze it and decide what to do with it. Turns out we needed
all three as a multicycle. If we had pipelined it we would not have met
the timing budget.
and output delay to your path. Plus your path must be broken
arbitrarily and it is not simple to pick the optimal points. By not
adding registers and using an enable on the one register, you allow the
full N clock cycles for the logic to settle. This was exactly how we
designed an ATM chip. Once the cell had been received we had three
clocks to analyze it and decide what to do with it. Turns out we needed
all three as a multicycle. If we had pipelined it we would not have met
the timing budget.
Of course, two observations:
1) Flip-flop setup and clk->Q combined are pretty low compared to
interconnect costs. EG, from the Spartan II datasheet, the additional
time if the flip-flop is the LUT output is ~2 ns. So even if your
design is running at 100 MHz in one of these parts, only 20% of your
time is going to the flops.
In the Virtex II its in the <1 ns range on the slowest speedgrade.
2) Retiming can place those registers in the right place. You can
either do the transformation by hand or use a tool, but I'm not sure
how well Synplify will handle retiming through preplaced blocks, and
the attempt to maintain initial conditions really hurts the power of
this transformation.
Nonetheless, it is possible, and NOT hard (given a timing model), to
move all the registers manually into the right place, given the
algorithm to solve the problem. If a block is feed forward, and you
just want to repipeline the block, the task is easier.
--
Nicholas C. Weaver nweaver_at_cs.berkeley.edu
rickman
Guest
Guest
Wed Sep 29, 2004 7:49 pm
"Nicholas C. Weaver" wrote:
Quote:
In article <3F2A868E.85807215_at_yahoo.com>,
rickman <spamgoeshere4_at_yahoo.com> wrote:
Not always true. Anytime you add a register, you have to add setup time
and output delay to your path. Plus your path must be broken
arbitrarily and it is not simple to pick the optimal points. By not
adding registers and using an enable on the one register, you allow the
full N clock cycles for the logic to settle. This was exactly how we
designed an ATM chip. Once the cell had been received we had three
clocks to analyze it and decide what to do with it. Turns out we needed
all three as a multicycle. If we had pipelined it we would not have met
the timing budget.
Of course, two observations:
1) Flip-flop setup and clk->Q combined are pretty low compared to
interconnect costs. EG, from the Spartan II datasheet, the additional
time if the flip-flop is the LUT output is ~2 ns. So even if your
design is running at 100 MHz in one of these parts, only 20% of your
time is going to the flops.
In the Virtex II its in the <1 ns range on the slowest speedgrade.
2) Retiming can place those registers in the right place. You can
either do the transformation by hand or use a tool, but I'm not sure
how well Synplify will handle retiming through preplaced blocks, and
the attempt to maintain initial conditions really hurts the power of
this transformation.
Nonetheless, it is possible, and NOT hard (given a timing model), to
move all the registers manually into the right place, given the
algorithm to solve the problem. If a block is feed forward, and you
just want to repipeline the block, the task is easier.
The point is, why bother spending the effort to do something that is
going to *slow* down the design and possibly break it? As in the
example I gave, we found it was not worth the effort in our design to
even consider adding the registers. Besides, they are not anything
remotely like free in a design that has a high utilization.
I guess you just don't like multi-cycle constraints. But I find they
are quite easy to use if used correctly.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Jeff Cunningham
Guest
Guest
Wed Sep 29, 2004 7:49 pm
rickman wrote:
Quote:
The point is, why bother spending the effort to do something that is
going to *slow* down the design and possibly break it? As in the
example I gave, we found it was not worth the effort in our design to
even consider adding the registers. Besides, they are not anything
remotely like free in a design that has a high utilization.
going to *slow* down the design and possibly break it? As in the
example I gave, we found it was not worth the effort in our design to
even consider adding the registers. Besides, they are not anything
remotely like free in a design that has a high utilization.
This mirrors my experience. In a recent FPGA design, I had to multiply
two signed 24 bit numbers. It seemed easier to implement it as a
multicycle path than to break it up by hand into pipelined stages.
Now if there is some tool that will insert the pipelining automatically
that is easy to use and doesn't cost $20K/seat I would like to hear
about it, because it is a small hassle to set up the multicycle timing
constraints.
JCC
Nicholas C. Weaver
Guest
Guest
Wed Sep 29, 2004 7:49 pm
In article <JIPWa.2842$GN6.2539_at_fe01.atl2.webusenet.com>,
Jeff Cunningham <jcc_at_sover.net> wrote:
Quote:
This mirrors my experience. In a recent FPGA design, I had to multiply
two signed 24 bit numbers. It seemed easier to implement it as a
multicycle path than to break it up by hand into pipelined stages.
Now if there is some tool that will insert the pipelining automatically
that is easy to use and doesn't cost $20K/seat I would like to hear
about it, because it is a small hassle to set up the multicycle timing
constraints.
two signed 24 bit numbers. It seemed easier to implement it as a
multicycle path than to break it up by hand into pipelined stages.
Now if there is some tool that will insert the pipelining automatically
that is easy to use and doesn't cost $20K/seat I would like to hear
about it, because it is a small hassle to set up the multicycle timing
constraints.
Altera's standard flow includes retiming, so if you turn it on and
place the registers at the start, they get moved forward into the
design.
Likewise, Synplify does this as well, and the Xilinx only version I
thought was 7K each.
The only (and moderate/significant) gotcha is that both tools
preserve initial condition/global set-reset semantics, which limits
the benefits which retiming achieves. For a large design (eg, a uP
core) this can be a significant limitation, but it may be OK for a
single smaller module.
Also, if you do have to do this by hand for some design piece (after
all, the result IS a pipelined, higher throughput design), the
retiming algorithm itself is not that bad, and can be simplified: as
you don't have to get an exact solution to the all-pairs shortest-path
problem, but just want to insure the correctness constraints (the
number of registers on each path are unchanged).
--
Nicholas C. Weaver nweaver_at_cs.berkeley.edu
Jim Wu
Guest
Guest
Wed Sep 29, 2004 7:49 pm
Assume you nailed down the MAC for calculating one element, to
calculate one
row at a time, you just add a 10:1 mux before the MAC and select
inputs for the next element after the current element is done and the
accumulator is cleared. A counter or a simple state machine can be
used to control the mux select signal. This will take at least 10
times longer to get all 100 elements.
Jim Wu
jimwu88NOOOSPAM_at_yahoo.com
http://www.geocities.com/jimwu88/chips
"walala" <mizhael_at_yahoo.com> wrote in message news:<bipbje$51c$1_at_mozo.cc.purdue.edu>...
Quote:
Dear all,
I want to design an arithmatic datapath unit for digital signal processing
using VHDL and/or Verilog.
The input are 5 elements(either sequential or parallel) each having 8 bits.
It needs to multiply each of these 5 inputs with a predefined constant
matrix(10x10, floating point scaled and round to integer). The output will
be a 10x10 matrix summing the above five matrices up, each element having 12
bits). So for each element of the matrix, I can have a MAC unit. The
internal computation will be 16 bits.
Hence for each 5 inputs x1, x2, x3, x4, x5, the output matrix
Y=x1*C1+x2*C2+x3*C3+x4*C4+x5*C5 where Y, C1, C2, C3, C4, C5 are matrices;
If I put an MAC for each element, I will have a purely parallel
architecture, but I need 100 16bits MAC units, which will be too resource
consuming.
I am considering to make a parallel-serial architecture, at each time, it
outputs one row, which will be 10x12 bits... so the output will be
row-by-row.
I also need to consider to streamlize the datapath operation. Since there
will be a stream of 5 elements input in a non-stop fashion, the output will
also be non-stop streaming. So after one row is outputted, that row can be
used for computation/storage of the results for the next 5 input elements.
I am ok so far in thinking... but further thinking makes me confused and
perplexed... how to do sequential timing control(how to what to do at which
cycle)? do I need to pipelining? how to design the architecture? I mean, I
know pipelining theoratically from one semester course, but now I am going
to implement one, I am totally lost...
Finally, how to program this? Is there any examples for this?
Please help me!
Thanks a lot,
-Walala
I want to design an arithmatic datapath unit for digital signal processing
using VHDL and/or Verilog.
The input are 5 elements(either sequential or parallel) each having 8 bits.
It needs to multiply each of these 5 inputs with a predefined constant
matrix(10x10, floating point scaled and round to integer). The output will
be a 10x10 matrix summing the above five matrices up, each element having 12
bits). So for each element of the matrix, I can have a MAC unit. The
internal computation will be 16 bits.
Hence for each 5 inputs x1, x2, x3, x4, x5, the output matrix
Y=x1*C1+x2*C2+x3*C3+x4*C4+x5*C5 where Y, C1, C2, C3, C4, C5 are matrices;
If I put an MAC for each element, I will have a purely parallel
architecture, but I need 100 16bits MAC units, which will be too resource
consuming.
I am considering to make a parallel-serial architecture, at each time, it
outputs one row, which will be 10x12 bits... so the output will be
row-by-row.
I also need to consider to streamlize the datapath operation. Since there
will be a stream of 5 elements input in a non-stop fashion, the output will
also be non-stop streaming. So after one row is outputted, that row can be
used for computation/storage of the results for the next 5 input elements.
I am ok so far in thinking... but further thinking makes me confused and
perplexed... how to do sequential timing control(how to what to do at which
cycle)? do I need to pipelining? how to design the architecture? I mean, I
know pipelining theoratically from one semester course, but now I am going
to implement one, I am totally lost...
Finally, how to program this? Is there any examples for this?
Please help me!
Thanks a lot,
-Walala
EdwardH
Guest
Guest
Wed Sep 29, 2004 7:49 pm
Employers always cite high salaries/costs (i.e. man-hour rates) as
justification for laying off or
outsourcing work. Who sets the standards as to what an ASIC/FPGA designer
is really worth. Currently it is market forces. Supply and demand. There
seems to be
others that aren't so subject to these forces. e.g my anecdotal evidence is
that
non-technical consultants still do well and what about the hugh (read
obscene) salaries
paid to many CEO's. Often I see articles here about CEO bonuses paid despite
the
fact that the company performed badly.
Our problem is that the relationship between our work/inventiveness and
company profits
is not easily measurable e.g. compared to say a salesman. When corporate
outcomes
are due to the sum of all employees, how can executives justify their
salaries. I have seen
companies succeed despite their bad management. Unfortunately the discussion
will come
back to market forces ....... What about outsourcing CEO functions to India?
Now
that would save some money! Sorry .... excuse my poor attempt at humour.
I have to admit a lot of ignorance and apathy when it comes to the market
and corporate ways but this whole discussion only has merit if we look at
ways to turn
this around. This is a problem amongst engineers where we don't look after
ourselves enough. Many industries are highly protected. e.g. in Australia
they regulate
the number of doctors by controlling the number that enter University
courses each year.
Not that I advocate this for our profession. Other industries are highly
unionised.
What can we do? Particularly since engineers in all countries want to work.
Since I don't live
in the US I don't want to see protectionism as a suggested solution. Are we
putting
enough pressure on organizations like the IEEE to look at the issue or lobby
politicians to ensure that they are aware of our problems.
"tbx135" <tbx135_at_msn.com> wrote in message
news:9dyMb.56074$V82.48313_at_newssvr31.news.prodigy.com...
Quote:
In the US we saw a hiring "frenzy" for technical workers up until about
2001. It was not uncommon to see 20-30% salary adjustments job to job or
even year to year. ASIC designers were asking over $100K and in many cases
and getting it, plus sign-on bonus. Life was good.
Then the telecomm bubble popped but many people still used the "roaring
90's" as the standard for what was normal. Historically it wasn't. Tech
salaries in the US had then worked up to an all time high. That labor
market
was largely driven by investment money pouring into the tech sector.
Outsourcing all kinds of technical work to Asia was done all through the
90's, the infrastructure was there already. Labor savings for US vs Asia
was
over 50% in some cases. ASIC talent, being the most costly (here in the
US),
got hit severely.
I think the story is right-on. Politicians are going to look at gross
numbers. They see increasing salaries and jobs. That doesn't mean evenly
and
across the board though. Many would just say you have to be flexible until
you can find the job you want. I don't like doing crummy work but I would
have to live with facts. The facts are that it's an employers market and
the
supply of engineers exceeds the demand. It's going to take time to correct
itself.
2001. It was not uncommon to see 20-30% salary adjustments job to job or
even year to year. ASIC designers were asking over $100K and in many cases
and getting it, plus sign-on bonus. Life was good.
Then the telecomm bubble popped but many people still used the "roaring
90's" as the standard for what was normal. Historically it wasn't. Tech
salaries in the US had then worked up to an all time high. That labor
market
was largely driven by investment money pouring into the tech sector.
Outsourcing all kinds of technical work to Asia was done all through the
90's, the infrastructure was there already. Labor savings for US vs Asia
was
over 50% in some cases. ASIC talent, being the most costly (here in the
US),
got hit severely.
I think the story is right-on. Politicians are going to look at gross
numbers. They see increasing salaries and jobs. That doesn't mean evenly
and
across the board though. Many would just say you have to be flexible until
you can find the job you want. I don't like doing crummy work but I would
have to live with facts. The facts are that it's an employers market and
the
supply of engineers exceeds the demand. It's going to take time to correct
itself.
Jerry
Guest
Guest
Wed Sep 29, 2004 7:49 pm
"Jerry" <nospam_at_nowhere.com> wrote in message
news:vucg41jtdc7040_at_corp.supernews.com...
Quote:
cut wages? then cut housing, food, insurance, automobile, taxes and
everything else my wages go to cover.
"tbx135" <tbx135_at_msn.com> wrote in message
news:WwjFb.7911$wn5.7443_at_newssvr33.news.prodigy.com...
Offshoring is the market saying that labor is over-priced. Supply/demand
is
a natural law and while everyone can talk a good game at "protecting"
jobs,
the truth is if you can't compete, your business and it's "protected"
jobs
go away. Want to keep your job? Cut wages to compete.
Maybe the US Senate will help sti the flow of jobs overseas.
everything else my wages go to cover.
"tbx135" <tbx135_at_msn.com> wrote in message
news:WwjFb.7911$wn5.7443_at_newssvr33.news.prodigy.com...
Offshoring is the market saying that labor is over-priced. Supply/demand
is
a natural law and while everyone can talk a good game at "protecting"
jobs,
the truth is if you can't compete, your business and it's "protected"
jobs
go away. Want to keep your job? Cut wages to compete.
Maybe the US Senate will help sti the flow of jobs overseas.
http://news.ft.com/servlet/ContentServer?pagename=FT.com/StoryFT/FullStory&c
=StoryFT&cid=1073281284712&p=1012571727088
Abhijit
Guest
Guest
Wed Sep 29, 2004 7:49 pm
I deleted all of the messages from the thread.
I have been reading all the messages and I would like to add my 2
paisa (since I live in India) worth to this discussion.
I am an Engineer from one of the premier institutes of India and
worked for 4.5 yrs in the valley before returning to India in 5 years
back. At that time I saw a lot of concenrs that the local companies
were hiring "foreigners" and local people are losing jobs. The fact is
that USA doesn't produce so many engineers so they have to depend upon
some other country. You can not expect highschool dropouts to do the
job for which I was hired. It is a fact that even after 2 years of my
return my old company used to call me and request me to work for them
as a consultant (with the same hourly rate as anyone would get in the
first world!). I used to think that all first world people are good
and think logically, but some of the discussions here really make me
sad.
The world moves this way: If any third world country take over 'high
tech silicon valley work' from USA then it will be their
responsibility to create new higher tech work and contribute to the
world. This is how the world has worked.
If you don't like jobs being send over to other countries (very small
%age though) then you should first stop hiring foreign engineers for
whom you did not spend a single penny on education. Alternatively you
should take 100 poor people for every engineer you take from a third
world country, you can not just take the best people from the poor
countries and continue to be the best. Pretty soon the poor country
will not have any money to produce good engineers to serve you.
Everything can not go your way, there are laws of nature. I think in
long run it would be good if some jobs move to India, in that case you
don't have to import people from there and increase the load on
natural resources because of the lifestyle differences.
I am sorry if I hurt anyone's feelings here...
Jonathan Bromley
Guest
Guest
Wed Sep 29, 2004 7:49 pm
"Abhijit" <chakrabarty_at_hotmail.com> wrote in message
news:f42ec3b1.0401290121.4d725835_at_posting.google.com...
Quote:
I have been reading all the messages and I would like to add my 2
paisa (since I live in India) worth to this discussion.
[...]
paisa (since I live in India) worth to this discussion.
[...]
Quote:
The world moves this way: If any third world country take over 'high
tech silicon valley work' from USA then it will be their
responsibility to create new higher tech work and contribute to the
world. This is how the world has worked.
If you don't like jobs being send over to other countries (very small
%age though) then you should first stop hiring foreign engineers for
whom you did not spend a single penny on education. Alternatively you
should take 100 poor people for every engineer you take from a third
world country, you can not just take the best people from the poor
countries and continue to be the best. Pretty soon the poor country
will not have any money to produce good engineers to serve you.
Everything can not go your way, there are laws of nature.
[...]
tech silicon valley work' from USA then it will be their
responsibility to create new higher tech work and contribute to the
world. This is how the world has worked.
If you don't like jobs being send over to other countries (very small
%age though) then you should first stop hiring foreign engineers for
whom you did not spend a single penny on education. Alternatively you
should take 100 poor people for every engineer you take from a third
world country, you can not just take the best people from the poor
countries and continue to be the best. Pretty soon the poor country
will not have any money to produce good engineers to serve you.
Everything can not go your way, there are laws of nature.
[...]
Well said, Abhijit.
It's interesting that the people who whinge loudest about
leakage of jobs to the developing world, thanks to
free-market forces, seem mostly to be inhabitants of the
nation that has most vigorously embraced free-market
economics when it suited them. Those of us who feel
uncomfortable with the unfettered free market can sit
back smugly and say "I told you so", whilst goggling
open-mouthed at the protectionism that is sometimes
applied by supposedly free-market economies throughout
the developed world.
The developing world can offer us (and by "us" here I mean
the whole world's economy, not just the West) a well-trained,
highly motivated workforce that can mobilise very large
numbers of employees at comparatively low cost. Those costs
will, of course, increase as nations such as India become
more prosperous overall, but that will take some considerable
time. If the economies of the West wish to compete
effectively without significantly impacting Western lifestyle,
they must find ways of working that *cannot* be made better
or cheaper by the application of lots of skilled, cheap people.
That last observation has dramatic conclusions for the
electronics design community. It means that we cannot and
must not go on using low-level design techniques; 30 Verilog
RTL-cutters in the US are unlikely to be competitive with 100
Verilog RTL-cutters in Bangalore at the same price. Instead
we must find ways to use the West's traditional skills,
including aggressive and creative application of the latest
academic developments to industrial problems, to make small
numbers of people much more productive. For people in our
field, that means embracing the highest-level design and
validation techniques at our disposal, instead of remaining
dedicated to the nuts/bolts/wires/registers vision of chip
design that's left over from fifteen years ago.
Quote:
I am sorry if I hurt anyone's feelings here...
Perceptive *and* courteous. It's a powerful combination.
Thanks for your insights.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley_at_doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
fabbl
Guest
Guest
Wed Sep 29, 2004 7:49 pm
I agree. Kids in the US are interested in being MBA's , lawyers and pop
stars. There is definitely no glamour being an engineer. Nor is it going to
make you rich.
Many masters and Ph.d. programs are filled with asian students. Your lucky
to see one or two Americans in any advanced technology degree programs. The
whole overseas/foreign out-source phenomena is due in large part to talent
shortages. I say the market will correct itself in time, but the India as a
major source of technical talent is here to stay.
Marco Fioretti
Guest
Guest
Wed Sep 29, 2004 7:49 pm
Abhijit wrote:
Quote:
I have been reading all the messages and I would like to add my 2
paisa (since I live in India) worth to this discussion.
I am sorry if I hurt anyone's feelings here...
I'm almost sure you didn't hurt the feelings of anybody with
common sense and the courage to be objective.
Very good summary of the problem and its causes. Well said.
Ciao,
Marco
Prasanna
Guest
Guest
Wed Sep 29, 2004 7:49 pm
"fabbl" <yttt_at_nukes.com> wrote in message news:<vxgSb.1995$9f6.1596_at_newssvr31.news.prodigy.com>...
Quote:
I agree. Kids in the US are interested in being MBA's , lawyers and pop
stars. There is definitely no glamour being an engineer. Nor is it going to
make you rich.
Many masters and Ph.d. programs are filled with asian students. Your lucky
to see one or two Americans in any advanced technology degree programs. The
whole overseas/foreign out-source phenomena is due in large part to talent
shortages. I say the market will correct itself in time, but the India as a
major source of technical talent is here to stay.
stars. There is definitely no glamour being an engineer. Nor is it going to
make you rich.
Many masters and Ph.d. programs are filled with asian students. Your lucky
to see one or two Americans in any advanced technology degree programs. The
whole overseas/foreign out-source phenomena is due in large part to talent
shortages. I say the market will correct itself in time, but the India as a
major source of technical talent is here to stay.
Mixed thoughts here...
Its not true that asians always the best. They are cheap labour and
they can settle down for anything better than their current living
standard. If US faces the nightmare of jobs moving offshore, for
countries like India where layoff was unheard of in history is now a
reality. Many asians are used to exploitation but not used to be
insecure. In US, we have unemployment benefit, social security etc.
and what can we expect from third world countries when it comes to
laws against capitalist giant companies. Hitech engineers become "Use
and throw" commodity.
For example, Companies like Wipro in India still do not share its
profits with employees and their major business is "bodyshopping". Its
chairman holds 85% stocks and yet they are listed on NASDAQ. It is
true this company does layoff when company does not do good to
preserve its profits.
On the other hand, think of H1 workers at US... When US throws them
out after 6 years what do you expect them to do ? Think of people who
never get their green cards and slave themselves for the "carrot".
How about for a change, US workers apply for a green card for
China/India and work for their US companies there and compete with
local talents... Does not sound lucrative ? Eh... We need some
introspection here when we say "All men are equal"...
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