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rickman
Guest

Wed Jun 21, 2017 5:18 am   



yudhvirsingh1607_at_gmail.com wrote on 6/20/2017 9:49 AM:
Quote:
On Thursday, April 4, 2002 at 12:53:23 AM UTC+5:30, Edwin Grigorian wrote:

sir i want to design a display using encoder in which i have to design a quiz buzzer ...in this once a person gets priority if two persons simulataneously hit the button..he will not get again and thus the other person gets priority...sir can you plzz tell me how to do it..i tried it using a flag in which i toggle it after each iteration...


You are replying to a 15 year old post.

What you describe is exactly how I would do it. The state of the flag
indicates which user gets priority. The point that is not entirely clear to
me is how the flag is changed. Is it only changed when the two buttons are
pressed simultaneously? Or every time the button is pressed?

--

Rick C


Guest

Sat Oct 14, 2017 4:19 am   



If you are a new guy to learning Verilog, you must learn easy code first.

thelandarian@gmail.com
Guest

Wed Oct 10, 2018 10:45 pm   



On Tuesday, 5 September 2000 23:41:22 UTC-7, jerry jones wrote:
Quote:
Hello,

I need to know if there are any good free Verilog Simulators.
Currently I am using Cadence Verilog at school but Cadence doesn't
seem to have a "student version" that I can download and use at home.

If anyone has any suggestions or web pages that they can direct me it
would be greatly appreciated.

Thanks

jjones


Sorry I'm about 18 years too late, but for those who are still searching, I just found a Verilog editor extension for the Eclipse IDE. The Eclipse IDE is a very handy tool in itself and is published under the GNU license, so it's more community-driven than Visual Studio. The plugin seems to be fully functional, so it seems to be a win-win for those of you still in need of a Verilog editor/simulator for your home.


Guest

Thu Oct 11, 2018 2:45 am   



On Wednesday, September 6, 2000 at 2:41:22 AM UTC-4, jerry jones wrote:
Quote:
Hello,

I need to know if there are any good free Verilog Simulators.
Currently I am using Cadence Verilog at school but Cadence doesn't
seem to have a "student version" that I can download and use at home.

If anyone has any suggestions or web pages that they can direct me it
would be greatly appreciated.


I use the Lattice Semiconductor tools which include a free copy of the Aldec Active-HDL simulator which supports both Verilog and VHDL. I don't know so much about Verilog, but if you want to use VHDL-2008 you have to enable that option in every new project.

Rick C.


Guest

Tue Nov 06, 2018 8:45 am   



from simulation point of view, Assign statements order are irrelevant and all are executed concurrently, while statements between begin and end in an always block are executed sequentially from top to bottom.

============
Muhammad Nasiri


Guest

Fri Jan 18, 2019 11:45 am   



`timescale 1ns / 1ns

////////////////////////////////////////////////////////////////////////////////
// Arbiter - Unit 1 has priority but does not pre-empt a unit 2 grant. //
////////////////////////////////////////////////////////////////////////////////

module arbiter
(
input wire REQ1, REQ2,
output reg gnt1, gnt2
);

initial begin
gnt1 = 0;
gnt2 = 0;
forever begin
@(REQ1 or REQ2); // requests change
gnt1 <= REQ1 && !REQ2 // no contention
|| REQ1 && REQ2 && !gnt2; // 1 has priority
gnt2 <= REQ2 && !REQ1 // no contention
|| REQ2 && REQ1 && gnt2; // no pre-emption
end
end

endmodule


////////////////////////////////////////////////////////////////////////////////
// Requester - At random intervals needs one or the other or both resources. //
////////////////////////////////////////////////////////////////////////////////

module requester
#(
parameter integer SEED=1
)
(
input wire GNTA, GNTB,
output reg REQA, REQB
);

// TO DO - Define a watchdog task that after a reasonable amount of time
// (the solution uses 17 ns) drops both request signals and disables
// the request loop. The request loop will immediately restart.



initial begin : REQUEST
integer seed;
seed = SEED;
REQA = 0;
REQB = 0;
forever begin : LOOP
#($dist_uniform(seed,1,3));
REQA = $random;
REQB = $random;
// TO DO - Change each wait statement to a parallel block that:
// - Enables the watchdog task
// - Waits for the grant and when it comes disables the task
if (REQA) wait (GNTA);
if (REQB) wait (GNTB);
end
end

endmodule


////////////////////////////////////////////////////////////////////////////////
// Test - Instantiates two requesting units and two responding arbiters //
////////////////////////////////////////////////////////////////////////////////

module test;

wire req1a, req1b, gnt1a, gnt1b;
wire req2a, req2b, gnt2a, gnt2b;

requester #(42) r1 ( gnt1a, gnt1b, req1a, req1b ); // requests A first
requester #(86) r2 ( gnt2b, gnt2a, req2b, req2a ); // requests B first
arbiter aa ( req1a, req2a, gnt1a, gnt2a ); // gives requester 1 priority
arbiter ab ( req2b, req1b, gnt2b, gnt1b ); // gives requester 2 priority

initial
begin : MONITOR
integer mcd;
$timeformat (-9,0,"",4);
mcd = $fopen("outfile.txt");
$fdisplay (mcd,"time r1 r2 g1 g2");
$fmonitor (mcd,"%t %b%b %b%b %b%b %b%b",
$time,req1a,req1b,req2a,req2b,gnt1a,gnt1b,gnt2a,gnt2b);
#99 $finish;
end

endmodule







//// this is my Verilog code....I want solution for some problem which is mention in command on the code..guys please help me

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