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Andy
Guest

Thu Feb 17, 2011 8:04 pm   



Yes, it is easy to write bad (unmaintainable) code in both vhdl and
verilog.

The point I was trying to make is that just using 7 or 3'd7 is just as
bad as "111" in far too many cases.

Why is it 7 instead of 5? What is significant about 7? Or is it just
"all bits are set"? Is it a maximum value, a minimum value, an initial
value, "everything is on", "everything is off", or what? Does/should
the value track something else? A constant's declaration can tell the
reader all of that with code that gets verified by the tool every time
it is run.

I actually agree with your comment about being reminded of the exact
number of bits every time it appears. The code should be written such
that if the exact number of bits needs to change, it should require as
few manual changes to as few places in the code as practical. In that
regard, 7 may be preferable to 3'd7, but not to a well-defined
constant.

Andy

unfrostedpoptart
Guest

Thu Feb 17, 2011 10:19 pm   



Almost any embedded numerical constants are a sign of bad code. As you wrote, it doesn't tell you what it means. They should almost always - except in extremely trivial cases - be predefined (e.g. header file) constants using macros, parameters, enums, etc.

Bernd Paysan
Guest

Tue Feb 22, 2011 2:10 pm   



On Donnerstag, 17. Februar 2011 04:08, unfrostedpoptart wrote:

Quote:
I would guess a majority of the people reading this group do FPGA work so
they can afford to be sloppy in their code and just redo it if they make a
size mistake that causes an error. However, if you're doing huge ASICs
that cost over $1million for NRE and to re-spin if you make a mistake, you
sure as hell better be sizing your constants and running every compile and
lint checker you can think of!

You are putting a straw man up. I've done >$1M ASICs, and of course one of
the actions you should take is to implement a prototype in an FPGA, which
allows to exercise your design much better than simulation. Certainly, you
*also* should do simulations to test your design under artificial, but
controlled border conditions. And finally, using other tools to gather
informations for you can't be wrong.

The impression you are generating however is that compile+lint do 90% of the
work to achieve a good design. Never. Closer to 1%, I'd say. "If it
compiles, it's good" is a typical VHDL attitude, and can't be further from
the truth. It's probably a psychological problem: "because it was hard to
compile, it now must be good", but that's false reasoning. Writing VHDL
properly is just so much harder than writing proper Verilog.

--
Bernd Paysan
"If you want it done right, you have to do it yourself!"
http://www.jwdt.com/~paysan/

unfrostedpoptart
Guest

Wed Feb 23, 2011 1:25 am   



On Tuesday, February 22, 2011 5:10:59 AM UTC-8, Bernd Paysan wrote:
Quote:
On Donnerstag, 17. Februar 2011 04:08, unfrostedpoptart wrote:

I would guess a majority of the people reading this group do FPGA work so
they can afford to be sloppy in their code and just redo it if they make a
size mistake that causes an error. However, if you're doing huge ASICs
that cost over $1million for NRE and to re-spin if you make a mistake, you
sure as hell better be sizing your constants and running every compile and
lint checker you can think of!

The impression you are generating however is that compile+lint do 90% of the
work to achieve a good design.

Not at all. I'm just saying one important part of having a good design database is that it's syntactically clean. I didn't give any percentages of how important this is versus other testing, but even if it's only 1%, that's still a big deal in the face of NRE/re-spin costs and time-to-market.

David

gabor
Guest

Fri Mar 18, 2011 3:06 pm   



On Friday, March 18, 2011 1:19:12 AM UTC-4, aldorus wrote:
Quote:
Thanks guys. I have to go re-read the section on wire/net and reg/int.
This assignment rules have me confused

I find that having a simplified view of Verilog as a
simulation language helps me understand the rules a
bit better. If you think like a simulator, then a
reg or integer implies that the simulator needs storage
to compute the current value. A wire does not need
storage because it is continuously assigned or
connected to some other value for which the simulator
already has storage. This has nothing to do with the
type of procedural block within which the reg or integer
is assigned. For example a "reg" does not necessarily
imply storage in the actual hardware. If you were to
translate the Verilog procedure to a C program, however
the "reg" would require a variable.

Hope that isn't more confusing than helpful.

-- Gabor


Guest

Sat Feb 09, 2013 10:21 am   



Try http://wavedrom.googlecode.com


Guest

Tue Jun 25, 2013 6:53 am   



On Tuesday, March 18, 2003 7:36:48 PM UTC+5:30, Apollo wrote:
Quote:
hello,everyone:

who can help introduce about Strict Priority scheduling algorithm?



Guest

Tue Sep 17, 2013 9:32 am   



Hi,

I want to found my image file width and height of pixels . please let me know if any sample source available links.

Nikolaos Kavvadias
Guest

Tue Sep 17, 2013 12:56 pm   



> I want to found my image file width and height of pixels . please let me know if any sample source available links.

Hi,

please stop spamming the forum with your homework/job task help requests.

If you really want to work with image formats, I suggest you learn about PBM, PGM, PPM which are essentially plain data. I have extended Martin J. Thompsons PGM package for PBM and PPM images (thanks MJT for the great package). I suggest you work your way through your problem doing something similar..


Guest

Fri Dec 13, 2013 1:24 pm   



Hi Hemi Thaker,

Thanks for a nice work. Could you please send me the tared version of verilog-preprocessor. It would be very helpfull to me.

Thanks & Regards
Anil

Gabor
Guest

Sun Dec 15, 2013 3:41 am   



On 12/13/2013 6:24 AM, anilk.gajjala_at_gmail.com wrote:
Quote:
Hi Hemi Thaker,

Thanks for a nice work. Could you please send me the tared version of verilog-preprocessor. It would be very helpfull to me.

Thanks & Regards
Anil


This must be some kind of record - responding to a 17-year-old thread
about adding features to Verilog, many of which have since been
incorporated into the language.

--
Gabor


Guest

Mon Feb 10, 2014 11:45 am   



On Monday, April 12, 1999 12:30:00 PM UTC+5:30, Liang Tao wrote:
Quote:
Hi,

I am a new learner of Verilog and want to study it from a big example,
I want to know if anyone know such an example, eg., a RISC with source code and
detailed document?

Thank you veru much.


hi
plz send me vhdl code for mux d full scan cell

rickman
Guest

Mon Apr 07, 2014 5:48 am   



Not trying to be a jerk, but have you considered asking in a Verilog
group? This is a VHDL group. I'm just sayin'...

Tell you what, I've cross posted it for you. :)

Rick


On 4/6/2014 5:40 PM, sandhya pochiraju wrote:
Quote:

Hi All, I have few questions in verilog. please can someone here help me understand this.


Let's say, db_count = debounce_cnt at 10th positive edge.
will "IF" condition in second always block be true at 10th positive edge?

or will "IF" condition in second always block be true at 11th positive edge? but on 11th positive edge db_count will be set to 0 by first always block.


what is order of operation between "IF" and "Case" ?
Though everything is in one always block and non blocking statements are used, "IF" and "Case" are two seperate blocks in themselves. Is the non-blocking behaviour of statements not confined seperately to "IF" and "Case" blocks? i.e. statements inside "IF" are non-blocking but are they non-blocking to statements inside "case" and vice versa?

Code:



`timescale 1 ns / 1 ns
module debounce (
//inputs
// what value is stored in pbtn_in and switch_in
input clk, // clock
input [3:0] pbtn_in, // pushbutton inputs
input [7:0] switch_in, // slider switch inputs

//outputs
output reg [3:0] pbtn_db = 3'h0, // debounced outputs of pushbuttons
output reg [7:0] swtch_db = 8'h0 // debounced outputs of slider switches
);
parameter simulate = 0;
// these are two ways to simulate.
// simulate is a parameter.
// what is the difference in two waits.

localparam debounce_cnt = simulate ? 22'd5 // debounce clock when simulating
: 22'd4_000_000; // debounce count when running on HW

//shift registers used to debounce switches and buttons
reg [21:0] db_count = 22'h0; //counter for debouncer
// 8 switches.
// 5 buttons.
reg [4:0] shift_pb0 = 5'h0, shift_pb1 = 5'h0, shift_pb2 = 5'h0, shift_pb3 = 5'h0, shift_pb4 = 5'h0;
reg [3:0] shift_swtch0 = 4'h0, shift_swtch1 = 4'h0, shift_swtch2 = 4'h0, shift_swtch3 = 4'h0;
reg [3:0] shift_swtch4 = 4'h0, shift_swtch5 = 4'h0, shift_swtch6 = 4'h0, shift_swtch7 = 4'h0;

// debounce clock
// at positive edge, count is incremented
always @(posedge clk)
begin
if (db_count == debounce_cnt) // it is 5 for simulation.
db_count <= 1'b0; //takes 40mS to reach 4,000,000
else
db_count <= db_count + 1'b1;
end

always @(posedge clk)
begin
// if this always and one is line 51 race condition.
// if 51 runs first, then db_count will be set to szero when below condition is true.
if (db_count == debounce_cnt) begin //sample every 40mS
//shift registers for pushbuttons
// i am shifting left once and doing a bitwise OR it with 0th bit of pbth_in
// why
// what is the value in pbtn_in
shift_pb0 <= (shift_pb0 << 1) | pbtn_in[0];
shift_pb1 <= (shift_pb1 << 1) | pbtn_in[1];
shift_pb2 <= (shift_pb2 << 1) | pbtn_in[2];
shift_pb3 <= (shift_pb3 << 1) | pbtn_in[3];
shift_pb4 <= (shift_pb4 << 1) | pbtn_in[4];

//shift registers for slider switches
// i am doing same operation here.
// all these happen at same time.
// what is the value in switch_in
shift_swtch0 <= (shift_swtch0 << 1) | switch_in[0];
shift_swtch1 <= (shift_swtch1 << 1) | switch_in[1];
shift_swtch2 <= (shift_swtch2 << 1) | switch_in[2];
shift_swtch3 <= (shift_swtch3 << 1) | switch_in[3];
shift_swtch4 <= (shift_swtch4 << 1) | switch_in[4];
shift_swtch5 <= (shift_swtch5 << 1) | switch_in[5];
shift_swtch6 <= (shift_swtch6 << 1) | switch_in[6];
shift_swtch7 <= (shift_swtch7 << 1) | switch_in[7];
end

//debounced pushbutton outputs
// if first four bits are zero then bit zero is set to 0
// if first four bits are one then bit zero is set to 1
case(shift_pb0) 4'b0000: pbtn_db[0] <= 0; 4'b1111: pbtn_db[0] <= 1; endcase
case(shift_pb1) 4'b0000: pbtn_db[1] <= 0; 4'b1111: pbtn_db[1] <= 1; endcase
case(shift_pb2) 4'b0000: pbtn_db[2] <= 0; 4'b1111: pbtn_db[2] <= 1; endcase
case(shift_pb3) 4'b0000: pbtn_db[3] <= 0; 4'b1111: pbtn_db[3] <= 1; endcase
case(shift_pb4) 4'b0000: pbtn_db[4] <= 0; 4'b1111: pbtn_db[4] <= 1; endcase

//debounced slider switch outputs
case(shift_swtch0) 4'b0000: swtch_db[0] <= 0; 4'b1111: swtch_db[0] <= 1; endcase
case(shift_swtch1) 4'b0000: swtch_db[1] <= 0; 4'b1111: swtch_db[1] <= 1; endcase
case(shift_swtch2) 4'b0000: swtch_db[2] <= 0; 4'b1111: swtch_db[2] <= 1; endcase
case(shift_swtch3) 4'b0000: swtch_db[3] <= 0; 4'b1111: swtch_db[3] <= 1; endcase
case(shift_swtch4) 4'b0000: swtch_db[4] <= 0; 4'b1111: swtch_db[4] <= 1; endcase
case(shift_swtch5) 4'b0000: swtch_db[5] <= 0; 4'b1111: swtch_db[5] <= 1; endcase
case(shift_swtch6) 4'b0000: swtch_db[6] <= 0; 4'b1111: swtch_db[6] <= 1; endcase
case(shift_swtch7) 4'b0000: swtch_db[7] <= 0; 4'b1111: swtch_db[7] <= 1; endcase
end
// if and case happen in parallel as it is non blocking statement. right.
// for simulation i am not waiting for as much as i am waiting for synthesis.
endmodule



--

Rick


Guest

Fri Apr 11, 2014 4:13 pm   



вторник, 22 февраля 2000 г., 12:00:00 UTC+4 пользователь Tanya Brethour написал:
Quote:
I am attempting to convert a MPEG decoder written in C to a Verilog version.
I am new to Verilog as you probably can guess Smile This is a senior design
project so.. I can not just find one already written in Verilog on the
Internet.

Does anyone have any links to translators or compilers to accomplish this
task?

Thanks Smile
Tanya


try to use russian project http://www.vsyn.ru (i hope they make english version)

Gabor
Guest

Mon Jun 02, 2014 7:12 am   



On 5/30/2014 9:53 PM, kaiyutony_at_gmail.com wrote:
Quote:
Any Help Will Be Appreciated!

I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value.

The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count)

Is there any logical error? Or is there any Verilog Error that I missed?

Thank you very much!

module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2);
input Clock, Reset;
input signed [3:0] pt_0, pt_1, pt_2, pt_3;
output [6:0] hex1, hex0, hex3, hex2;

wire signed [6:0] count;
wire signed [6:0] maxcount;
score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);

display(count, maxcount, hex1, hex0, hex3, hex2);

endmodule

module display (count, maxcount, hex1, hex0, hex3, hex2);
input [6:0] count, maxcount;
output [6:0] hex1, hex0, hex3, hex2;

wire [4:0] unit, unit_m;
wire [4:0] tens, tens_m;

assign unit = count % 10;
assign tens = count / 10;

assign unit_m = count % 10;
assign tens_m = count / 10;

seg7 ud (unit, hex0);
seg7 td (tens, hex1);
seg7 umd (unit_m, hex2);
seg7 tmd (tens_m, hex3);


endmodule

module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);
input Clock, Reset;
//input signed [3:0] sum;
input [3:0] pt_0, pt_1, pt_2, pt_3;
parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110;
//input zero, negative, carry, overflow;

output signed [6:0] count, maxcount;
reg signed [6:0] count, maxcount;

////wire PS;
//reg NS;

always @(posedge Clock)
if (Reset) begin
count <= 7'b0;
maxcount <= 7'b0;
end else begin
if (count > maxcount) begin
maxcount <= count;
end
if (pt_0 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_0;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_1 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_1;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_2 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_2;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_3 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_3;
if (count > 7'b100010) begin
count <= 7'b0;
end
end
end
endmodule


There's nothing obvious to me. Is it failing in behavioral simulation
or only in hardware (you did simulate, right)?

I've had issues with signed arithmetic in Verilog, but in this
case count and maxcount have the same type, so I don't see
an issue with the logic. Could there be a problem with synchronization
to the clock? All inputs need to be synchronous to the clock,
especially Reset. Obviously a Reset pulse could cause maxcount
to go down.

--
Gabor

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