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arko
Guest
Guest
Sat Sep 13, 2008 9:31 pm
Quote:
sharp_at_cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
I don't suppose there are plans to add this functionality to irun 8.2?
Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.
At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.
(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
arko
Guest
Guest
Sat Sep 13, 2008 9:31 pm
Quote:
sharp_at_cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
I don't suppose there are plans to add this functionality to irun 8.2?
Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.
At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.
(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
arko
Guest
Guest
Sat Sep 13, 2008 9:31 pm
Quote:
sharp_at_cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
I don't suppose there are plans to add this functionality to irun 8.2?
Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.
At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.
(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
arko
Guest
Guest
Sat Sep 13, 2008 9:31 pm
Quote:
sharp_at_cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
I don't suppose there are plans to add this functionality to irun 8.2?
Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.
At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.
(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
arko
Guest
Guest
Sat Sep 13, 2008 9:31 pm
Quote:
sharp_at_cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
I don't suppose there are plans to add this functionality to irun 8.2?
Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.
At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.
(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
arko
Guest
Guest
Sat Sep 13, 2008 9:31 pm
Quote:
sharp_at_cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51_at_u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.
NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
I don't suppose there are plans to add this functionality to irun 8.2?
Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.
At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.
(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
Mike Lewis
Guest
Guest
Thu Sep 25, 2008 4:42 pm
"Fei Liu" <fei.liu_at_gmail.com> wrote in message news:gbg77f$133$1_at_aioe.org...
Quote:
Hello, I have a problem here I can't seem to fix. I have incoming data on
the serial port, I have a RAM module, I'd like to store the incoming data
into RAM. Ram module has an address pin (addr), serial module has data and
data_ready (single clock pulse) pin. I have a bytecount register to keep
track of the address. Here is a code snippet:
always @(posedge clk) begin
if(state == s_recv && data_ready) begin
addr = bytecount;
bytecount = bytecount + 1;
end
end
Here is my problem, I sent over "abcdefg", when I read back, I get
"bbcdefg"; if I sent over "hijklmn" I get back "iijklmn".
I know there is racing issue with my 2 statements in the above code
snippet, I can't seem to find a better way to handle this. Note that I
would potentially use the module to receive data from a higher speed
interface so a simple delay+bytecount_inc is not an optimal solution here.
What's the correct way to handle this situation? Thanks,
Fei
the serial port, I have a RAM module, I'd like to store the incoming data
into RAM. Ram module has an address pin (addr), serial module has data and
data_ready (single clock pulse) pin. I have a bytecount register to keep
track of the address. Here is a code snippet:
always @(posedge clk) begin
if(state == s_recv && data_ready) begin
addr = bytecount;
bytecount = bytecount + 1;
end
end
Here is my problem, I sent over "abcdefg", when I read back, I get
"bbcdefg"; if I sent over "hijklmn" I get back "iijklmn".
I know there is racing issue with my 2 statements in the above code
snippet, I can't seem to find a better way to handle this. Note that I
would potentially use the module to receive data from a higher speed
interface so a simple delay+bytecount_inc is not an optimal solution here.
What's the correct way to handle this situation? Thanks,
Fei
Try replacing = with <=
Jonathan Bromley
Guest
Guest
Sun Apr 05, 2009 10:05 am
On Sat, 4 Apr 2009 08:54:19 -0700 (PDT), unfrostedpoptart wrote:
Quote:
This has been giving me headaches as I start using SV Interfaces.
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.
Does anyone have an easy solution to this?
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.
Does anyone have an easy solution to this?
By default, VCS does compilation and elaboration in a
single step (the "vcs" command). In Cadence and Mentor
simulators, you can run an independent compilation step
(ncvlog, vlog) that syntax-checks the module(s) but does
not attempt to do elaboration. I believe the same thing
can be done in VCS, and I *think* the command is "vlogan",
but you'll need to check the docs yourself.
Beware that this sort of single-module compilation doesn't
buy you a lot in Verilog or SV (unlike VHDL, where compiling
a module successfully is pretty much a guarantee that it can
be elaborated correctly). If your module has an interface-
type port and you compile it, there is no check that the
interface has the form that your code expects. See my recent
rant-paper at DVCon for further evidence of how this stuff
rather easily raises my blood pressure.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley_at_MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Guest
Sun Apr 26, 2009 10:37 pm
On Apr 18, 5:05 am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
Quote:
uraniumore...@gmail.com wrote:
Hello All,
I have a question regarding programming the Spartan 3AN. I have a bit
file that I would like to program on my board, and would like to run
every time I turn on the FPGA. I know it can be easily done, but I
just don't know the process.
Start impact with a jtag dongle connected to your board, and when the 3AN is
recognized in your jtag chain. click right on the device. There is an option
(in recent impact versions) to program the on-chip flash.
Be sure the FPGA Mode pins are connected right. Check UG332.
Bye
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Hello All,
I have a question regarding programming the Spartan 3AN. I have a bit
file that I would like to program on my board, and would like to run
every time I turn on the FPGA. I know it can be easily done, but I
just don't know the process.
Start impact with a jtag dongle connected to your board, and when the 3AN is
recognized in your jtag chain. click right on the device. There is an option
(in recent impact versions) to program the on-chip flash.
Be sure the FPGA Mode pins are connected right. Check UG332.
Bye
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
I cannot get the pin connected right. Which pins do I need to connect
to get the SPANTAN 3AN to program my internal flash? Note that I am
trying to configure the board so that whenever I restart the board
the .bit fill gets loaded automatically.
Guest
Sun Apr 26, 2009 11:32 pm
On Apr 26, 12:37 pm, uraniumore...@gmail.com wrote:
Quote:
On Apr 18, 5:05 am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
uraniumore...@gmail.com wrote:
Hello All,
I have a question regarding programming the Spartan 3AN. I have a bit
file that I would like to program on my board, and would like to run
every time I turn on the FPGA. I know it can be easily done, but I
just don't know the process.
Start impact with a jtag dongle connected to your board, and when the 3AN is
recognized in your jtag chain. click right on the device. There is an option
(in recent impact versions) to program the on-chip flash.
Be sure the FPGA Mode pins are connected right. Check UG332.
Bye
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
I cannot get the pin connected right. Which pins do I need to connect
to get the SPANTAN 3AN to program my internal flash? Note that I am
trying to configure the board so that whenever I restart the board
the .bit fill gets loaded automatically.- Hide quoted text -
- Show quoted text -
darmstadt.de> wrote:
uraniumore...@gmail.com wrote:
Hello All,
I have a question regarding programming the Spartan 3AN. I have a bit
file that I would like to program on my board, and would like to run
every time I turn on the FPGA. I know it can be easily done, but I
just don't know the process.
Start impact with a jtag dongle connected to your board, and when the 3AN is
recognized in your jtag chain. click right on the device. There is an option
(in recent impact versions) to program the on-chip flash.
Be sure the FPGA Mode pins are connected right. Check UG332.
Bye
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
I cannot get the pin connected right. Which pins do I need to connect
to get the SPANTAN 3AN to program my internal flash? Note that I am
trying to configure the board so that whenever I restart the board
the .bit fill gets loaded automatically.- Hide quoted text -
- Show quoted text -
Okay, I have figured it out.
I read http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf,
and I found out that after you program the flash memory, disconnect
the power adapter and remove the jumpers from J23, J25, and J16, and
then re-connect the power adapter.
Bingo!
Thanks,
Jeremy Bennett
Guest
Guest
Fri Jul 24, 2009 9:11 am
On Thu, 23 Jul 2009 07:31:31 -0700, Kenneth Brun Nielsen wrote:
Quote:
Can I save the state of a simulation using Icarus Verilog simulator?
I found the $save command in Google, but it doen't seem to work in
Icarus (vvp).
"
$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors. "
Any alternatives in Icarus?
I found the $save command in Google, but it doen't seem to work in
Icarus (vvp).
"
$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors. "
Any alternatives in Icarus?
Hi Kenneth,
$save is an optional part of Verilog (at least Verilog 2001). It's in
Annex C of the standard (IEEE 1364-2001). I can't find explicit reference
to it in the Icarus Verilog documentation.
You might find it useful to ask the Icarus Verilog developer's mailing
list about this issue: https://lists.sourceforge.net/lists/listinfo/
iverilog-devel. If the feature isn't there, it's open source, so you
could always add it yourself
.
HTH,
Jeremy
Stephen Williams
Guest
Guest
Mon Jul 27, 2009 2:39 pm
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Kenneth Brun Nielsen wrote:
Quote:
Can I save the state of a simulation using Icarus Verilog simulator?
I found the $save command in Google, but it doen't seem to work in
Icarus (vvp).
$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors.
I found the $save command in Google, but it doen't seem to work in
Icarus (vvp).
$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors.
It's not implemented in Icarus Verliog (it's an optional part of
the standard) and implementing it would be pretty involved. If you
would like to see it in the future, discuss it in the iverilog-devel
mailing list, and/or add a feature request tracker item.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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iD8DBQFKba33rPt1Sc2b3ikRAs6BAJ9On+Q705x3r632MW0iNpQmh+YIWQCgytHB
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Allan Herriman
Guest
Guest
Tue Jul 28, 2009 4:22 pm
On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
Quote:
On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph_at_yahoo.com> wrote:
Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
Altera FPGA tools?
I'd also be very interested in Core7 vs Phenom II performance too (45nm
AMD ie Phenom II 955 etc.)
schvantzkoph_at_yahoo.com> wrote:
Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
Altera FPGA tools?
I'd also be very interested in Core7 vs Phenom II performance too (45nm
AMD ie Phenom II 955 etc.)
We just got a new i7 machine for FPGA builds. It tested at just over
twice as fast as our high-end AMD box that was 2-3 years old.
I will publish the results in this ng within a week or two, assuming I
can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx,
flexlm was a really good move.)
Regards,
Allan
General Schvantzkoph
Guest
Guest
Tue Jul 28, 2009 5:04 pm
On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:
Quote:
On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph_at_yahoo.com> wrote:
Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
Altera FPGA tools?
I'd also be very interested in Core7 vs Phenom II performance too (45nm
AMD ie Phenom II 955 etc.)
We just got a new i7 machine for FPGA builds. It tested at just over
twice as fast as our high-end AMD box that was 2-3 years old.
I will publish the results in this ng within a week or two, assuming I
can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx,
flexlm was a really good move.)
Regards,
Allan
On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph_at_yahoo.com> wrote:
Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
Altera FPGA tools?
I'd also be very interested in Core7 vs Phenom II performance too (45nm
AMD ie Phenom II 955 etc.)
We just got a new i7 machine for FPGA builds. It tested at just over
twice as fast as our high-end AMD box that was 2-3 years old.
I will publish the results in this ng within a week or two, assuming I
can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx,
flexlm was a really good move.)
Regards,
Allan
What's the clock rate on each machine? iCore7 motherboards and processors
are twice as expensive as Core2 motherboards and processors, and
mainstream Core2s have a higher clock rate than iCore7s, so the clock
rate normalized performance is what's important.
Jason Zheng
Guest
Guest
Tue Jul 28, 2009 5:42 pm
On 28 Jul 2009 16:04:32 GMT
General Schvantzkoph <schvantzkoph_at_yahoo.com> wrote:
Quote:
On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:
On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph_at_yahoo.com> wrote:
Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx
and Altera FPGA tools?
I'd also be very interested in Core7 vs Phenom II performance too
(45nm AMD ie Phenom II 955 etc.)
We just got a new i7 machine for FPGA builds. It tested at just
over twice as fast as our high-end AMD box that was 2-3 years old.
I will publish the results in this ng within a week or two,
assuming I can ever get the licensing for ISE 11.2 running on it.
(Thanks Xilinx, flexlm was a really good move.)
Regards,
Allan
What's the clock rate on each machine? iCore7 motherboards and
processors are twice as expensive as Core2 motherboards and
processors, and mainstream Core2s have a higher clock rate than
iCore7s, so the clock rate normalized performance is what's important.
On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph_at_yahoo.com> wrote:
Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx
and Altera FPGA tools?
I'd also be very interested in Core7 vs Phenom II performance too
(45nm AMD ie Phenom II 955 etc.)
We just got a new i7 machine for FPGA builds. It tested at just
over twice as fast as our high-end AMD box that was 2-3 years old.
I will publish the results in this ng within a week or two,
assuming I can ever get the licensing for ISE 11.2 running on it.
(Thanks Xilinx, flexlm was a really good move.)
Regards,
Allan
What's the clock rate on each machine? iCore7 motherboards and
processors are twice as expensive as Core2 motherboards and
processors, and mainstream Core2s have a higher clock rate than
iCore7s, so the clock rate normalized performance is what's important.
Clock rates is just an artificial number; I'd be more interested in
performance normalized to non-recurring cost (purchase price) and
operating cost (power consumption).
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