NCsim with verilog and VHDL

I have a VHDL file that I want to instantiate into a verilog
testbench. I looked through
Cadence sourcelink to see how to integrate verilog and VHDL using
NCsim simulator.
And I don't find any information. Anyone know of a "howto" for
getting verilog/VHDL
to work in NCsim.

Compile your VHDL with ncvhdl and your Verilog with ncvlog. Elaborate your
testbench with ncelab and then run the simulation on the snapshot with ncsim.
You're done!

If you want more information, please be more specific.

OK thanks, that makes sense. When you compile the verilog and VHDL
modules,
do the binaries all land in the same INCA_libs directory ?

Then I have to figure out how to point to both types of compiled
modules in the elaborate step.

I looked on Cadence sourcelink, and there is no information on ncelab
for mixed verilog/VHDL.

Compile your VHDL with ncvhdl and your Verilog with ncvlog. Elaborate your
testbench with ncelab and then run the simulation on the snapshot with ncsim.
You're done!

If you want more information, please be more specific.

Yes, unless you specify another library in the command line.

Then I have to figure out how to point to both types of compiled
modules in the elaborate step.

What do you mean?

I looked on Cadence sourcelink, and there is no information on ncelab
for mixed verilog/VHDL.

That's mainly because this is natively handled, I mean, nothing special should
be done