Wed Dec 17, 2008 1:44 pm
I wish to do a nanosim fast spice simulation.
I am confused about how to do this.
I have the SPEF file, .mod file, the gate-level verilog netlist and a
Is it possible to use the test-bench directly or must I generate
a .vcd file and then convert the .vcd file to .vec file with the
How do i set my power supply voltage etc?
Please help, I am totally lost!
Thu Apr 21, 2011 12:46 pm