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elektroda.net NewsGroups Forum Index - VHDL Language - **mxn bit mulplication maps how many gates?**

Guest

Thu Mar 03, 2016 1:25 pm

in asic, given a 8x8b unsigned multiplication, how can i estimate the gates using design compiler?

Is there an experient value about mxn bit mul to gates number?

Guest

Thu Mar 03, 2016 11:44 pm

On 3/3/2016 6:25 AM, Yang Luo wrote:

in asic, given a 8x8b unsigned multiplication, how can i estimate the gates using design compiler?

Is there an experient value about mxn bit mul to gates number?

Is there an experient value about mxn bit mul to gates number?

If both inputs are variables, the number of gates is well defined. You

know what half and full adders are, right? Try synthesizing a few

examples in your favorite tool and measure the gates. It should be very

easy to come up with a general formula.

--

Rick

Guest

Fri Mar 11, 2016 2:17 am

so, different technology（like 22nm,40nm）have different result gates when using dc synthesis? is there a relationship between technology and gates? i use dc to synthesis a two variable input 8*8 mul, it get an erea about xx um^2, how can i change the scripts to get gate number ?

elektroda.net NewsGroups Forum Index - VHDL Language - **mxn bit mulplication maps how many gates?**