bbrady
Guest
Wed Jan 27, 2010 3:21 am
Hi All,
I've come across some VHDL that I don't understand. The snippet is
below:
req_resp(0 to 1) <= adder_resp(0 to 1) or shift_resp(0 to 1) WHEN
(adder_resp(0 to 1) /= "00"
or shift_resp(0 to 1) /= "00") ELSE
"10" WHEN (inv_op1_tag(0) = '1') ELSE
"00";
The part that I'm confused on is "adder_resp(0 to 1) or shift_resp(0
to 1)" directly after "<=" and before the first "WHEN". What exactly
does this mean? I've looked through the VHDL standard and haven't seen
any bitwise operators. Furthermore, the "or" operator is a logical
operator, so I can't figure out why it would be used on bit vectors.
Is the logical or doing some kind of behind-the-scene evaluation of
adder_resp(0 to 1) before it makes the assignment (e.g., if adder_resp
= 00 then use the RHS of the logical or)?
I typically work on Verilog and haven't worked with VHDL in close to
10 years, so I may be forgetting something obvious, or maybe this is
bogus code (although, it would surprise me if it were). Any help would
be greatly appreciated.
Thanks!
bb
Kenn Heinrich
Guest
Wed Jan 27, 2010 4:15 am
bbrady <bryan.brady_at_gmail.com> writes:
Quote:
Hi All,
I've come across some VHDL that I don't understand. The snippet is
below:
req_resp(0 to 1) <= adder_resp(0 to 1) or shift_resp(0 to 1) WHEN
(adder_resp(0 to 1) /= "00"
or shift_resp(0 to 1) /= "00") ELSE
"10" WHEN (inv_op1_tag(0) = '1') ELSE
"00";
The part that I'm confused on is "adder_resp(0 to 1) or shift_resp(0
to 1)" directly after "<=" and before the first "WHEN". What exactly
does this mean?
That part is an expression yielding a length 2 vector just like your
LHS. It's presumably the bitwise-or of the two arguments (unless
someone is playing mind-games on you with operator overloading).
Quote:
I've looked through the VHDL standard and haven't seen
any bitwise operators. Furthermore, the "or" operator is a logical
operator, so I can't figure out why it would be used on bit vectors.
Don;t forget operator and function overloading. In VHDL, there's a
predefined bitwise "or" function also defined on 1-D arrays
(i.e. vectors) of type boolean, bit, and also std_logic_vector. These
come from either the standard library or the std_logic_1164 package
that you normally refer to at the top of each file.
Quote:
Is the logical or doing some kind of behind-the-scene evaluation of
adder_resp(0 to 1) before it makes the assignment (e.g., if adder_resp
= 00 then use the RHS of the logical or)?
No. This code is roughly equal to the following pseudocode
if ( (adder_resp(0 to 1) /= "00")
or (shift_resp(0 to 1) /= "00"))
then
req_resp(0 to 1) <= adder_resp(0 to 1) or shift_resp(0 to 1);
elsif (inv_op1_tag(0) = '1') then
req_resp(0 to 1) <= "10";
else
req_resp(0 to 1) <= "00";
end if;
Where the "or" in the condition of the first "if" is a simple boolean
or, while the "or" in the first signal assignment is a bitwise
"or". The context distinguishes them.
- Kenn
bbrady
Guest
Wed Jan 27, 2010 5:47 am
Quote:
Don;t forget operator and function overloading. In VHDL, there's a
predefined bitwise "or" function also defined on 1-D arrays
(i.e. vectors) of type boolean, bit, and also std_logic_vector. These
come from either the standard library or the std_logic_1164 package
that you normally refer to at the top of each file.
Where the "or" in the condition of the first "if" is a simple boolean
or, while the "or" in the first signal assignment is a bitwise
"or". The context distinguishes them.
This is what I was missing. This makes sense now -- I couldn't believe
that there were no bitwise operators defined. It turns out that I was
looking for answers in the wrong place.
Thanks a lot!