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Sylvia Else
Guest

Wed Jan 11, 2017 7:49 am   



As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Sylvia.


Guest

Wed Jan 11, 2017 7:49 am   



On Wednesday, January 11, 2017 at 11:50:02 AM UTC+11, Sylvia Else wrote:
Quote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?


Probably the VIPER processor.

https://en.wikipedia.org/wiki/VIPER_microprocessor

The UK Royal Radar Establishment claimed that the chip had been designed using a formalism that allowed each stage of the development to be mathematically tested for errors and mathematically proven to be error free. I don't know what approach they used - the one I've encountered (but never came close to using) was

https://en.wikipedia.org/wiki/Z_notation

No software guy I've run into take it seriously, but most of them were transparently cowboys, and the rest put their faith in simpler rules.

--
Bill Sloman, Sydney

rickman
Guest

Wed Jan 11, 2017 7:54 am   



On 1/10/2017 7:49 PM, Sylvia Else wrote:
Quote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?


555 timer? I know many chips have part numbers of xxxA and xxxB which
makes you think there must have been at least one before, no?

--

Rick C

Jim Thompson
Guest

Wed Jan 11, 2017 8:03 am   



On Wed, 11 Jan 2017 11:49:55 +1100, Sylvia Else
<sylvia_at_not.at.this.address> wrote:

Quote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Sylvia.


You are apparently judging chips only from a digital chip POV.

Over the past 55+ years I've churned out several hundred Analog
chips... only 2 out of that amount did I @#$% up.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Jim Thompson
Guest

Wed Jan 11, 2017 8:05 am   



On Tue, 10 Jan 2017 18:03:05 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon_at_On-My-Web-Site.com> wrote:

Quote:
On Wed, 11 Jan 2017 11:49:55 +1100, Sylvia Else
sylvia_at_not.at.this.address> wrote:

As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Sylvia.

You are apparently judging chips only from a digital chip POV.

Over the past 55+ years I've churned out several hundred Analog
chips... only 2 out of that amount did I @#$% up.

...Jim Thompson


And more than half of that count were done BC (before CAD and
simulators).

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

bitrex
Guest

Wed Jan 11, 2017 8:30 am   



On 01/10/2017 10:52 PM, Johann Klammer wrote:
Quote:
On 01/11/2017 01:54 AM, rickman wrote:
On 1/10/2017 7:49 PM, Sylvia Else wrote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

555 timer? I know many chips have part numbers of xxxA and xxxB which makes you think there must have been at least one before, no?

I believe their reset input is historically broken, tho...
Does it still count as error-free?


Yep, the 555 timer's reset line is bugged by the standards of some; it
won't interface "correctly" like a logic device:

http://www.electroschematics.com/7195/quirky-555-timer-reset-function/

rickman
Guest

Wed Jan 11, 2017 8:30 am   



On 1/10/2017 8:55 PM, bill.sloman_at_ieee.org wrote:
Quote:
On Wednesday, January 11, 2017 at 11:50:02 AM UTC+11, Sylvia Else wrote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Probably the VIPER processor.

https://en.wikipedia.org/wiki/VIPER_microprocessor

The UK Royal Radar Establishment claimed that the chip had been designed using a formalism that allowed each stage of the development to be mathematically tested for errors and mathematically proven to be error free. I don't know what approach they used - the one I've encountered (but never came close to using) was

https://en.wikipedia.org/wiki/Z_notation

No software guy I've run into take it seriously, but most of them were transparently cowboys, and the rest put their faith in simpler rules.


How can any system be used to design error free chips when humans are
involved. The North Anna nuclear power plant was supposed to have no
single point of failure. When the earthquake shook the plant into
shutdown one of the diesel generators failed to be replaced by a backup.

When they looked into the cause of the failure they found a head gasket
had been installed incorrectly because the procedure for installation
was faulty. There's your single point of failure. If the procedure is
faulty, it can cause *every* generator to fail.

Humans were involved, so mistakes were made.

--

Rick C

Johann Klammer
Guest

Wed Jan 11, 2017 8:30 am   



On 01/11/2017 01:54 AM, rickman wrote:
Quote:
On 1/10/2017 7:49 PM, Sylvia Else wrote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

555 timer? I know many chips have part numbers of xxxA and xxxB which makes you think there must have been at least one before, no?

I believe their reset input is historically broken, tho...
Does it still count as error-free?

David Brown
Guest

Wed Jan 11, 2017 3:59 pm   



On 11/01/17 01:49, Sylvia Else wrote:
Quote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Sylvia.


When the Inmos "transputer" chip was designed (I don't remember which
particular chip), the design was independently checked by a formal
mathematical proof done by a university team, and by exhaustive checking
of every combination for all instructions (using large numbers of chips
running in parallel for half a year or so).

The two checks found exactly the same set of errors, which were then
corrected.


Of course, there might have been problems or errata on issues other than
the logical operation of the cpu.

Tom Gardner
Guest

Wed Jan 11, 2017 4:37 pm   



On 11/01/17 01:55, bill.sloman_at_ieee.org wrote:
Quote:
On Wednesday, January 11, 2017 at 11:50:02 AM UTC+11, Sylvia Else wrote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Probably the VIPER processor.

https://en.wikipedia.org/wiki/VIPER_microprocessor

The UK Royal Radar Establishment claimed that the chip had been designed using a formalism that allowed each stage of the development to be mathematically tested for errors and mathematically proven to be error free. I don't know what approach they used -


LCF-LSM and ELLA. Messrs Cullyer and Pyggot.
http://oai.dtic.mil/oai/oai?verb=getRecord&metadataPrefix=html&identifier=ADA168248

Marko Rauhamaa
Guest

Wed Jan 11, 2017 5:23 pm   



David Brown <david.brown_at_hesbynett.no>:

Quote:
When the Inmos "transputer" chip was designed (I don't remember which
particular chip), the design was independently checked by a formal
mathematical proof done by a university team,


Mathematical proofs are much like program code. In fact, it resembles
assembly language code that is run in the human brain. Mistakes are easy
to make.

Of course, automated proof checking alleviates this risk quite a bit,
but you can still make mistakes in your modeling.

Now, automated proof checking *is* awe-inspiring: <URL:
http://us.metamath.org/mpeuni/fta.html>. No steps are skipped. For
example, proving "2 + 2 = 4" involves 2,452 subtheorems: <URL:
http://us.metamath.org/mpeuni/mmset.html#trivia>. And look at this gem:
<URL: http://us.metamath.org/mpeuni/dfbi1gb.html>!


Marko

David Brown
Guest

Wed Jan 11, 2017 6:15 pm   



On 11/01/17 11:23, Marko Rauhamaa wrote:
Quote:
David Brown <david.brown_at_hesbynett.no>:

When the Inmos "transputer" chip was designed (I don't remember which
particular chip), the design was independently checked by a formal
mathematical proof done by a university team,

Mathematical proofs are much like program code. In fact, it resembles
assembly language code that is run in the human brain.


No, they are not like program code or assembly, and they do not "run in
the human brain" like on a computer.

> Mistakes are easy to make.

Mistakes can certainly be made. It is also possible to write proofs
without making mistakes. In this particular case, the same design
issues were spotted by both those doing the mathematical verification,
and those doing the exhaustive testing of the hardware.

Quote:

Of course, automated proof checking alleviates this risk quite a bit,
but you can still make mistakes in your modeling.


True.

Quote:

Now, automated proof checking *is* awe-inspiring: <URL:
http://us.metamath.org/mpeuni/fta.html>. No steps are skipped. For
example, proving "2 + 2 = 4" involves 2,452 subtheorems: <URL:
http://us.metamath.org/mpeuni/mmset.html#trivia>. And look at this gem:
URL: http://us.metamath.org/mpeuni/dfbi1gb.html>!


That all depends on the kind of proofs you are looking for, what
definitions you are using, what axioms you are using, and so on. In
particular, this example is using complex numbers - the proof of 2 + 2 =
4 in natural numbers is far simpler. The example is also used to write
things in the way that generates the most impressive numbers, with every
sub-theorem expanded fully at every step, rather than the way proofs are
/really/ done by proving each sub-theorem only once.

Sylvia Else
Guest

Wed Jan 11, 2017 6:37 pm   



On 11/01/2017 7:59 PM, David Brown wrote:
Quote:
On 11/01/17 01:49, Sylvia Else wrote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Sylvia.

When the Inmos "transputer" chip was designed (I don't remember which
particular chip), the design was independently checked by a formal
mathematical proof done by a university team, and by exhaustive checking
of every combination for all instructions (using large numbers of chips
running in parallel for half a year or so).

The two checks found exactly the same set of errors, which were then
corrected.


Of course, there might have been problems or errata on issues other than
the logical operation of the cpu.


Even with proofs, you need to be sure that all the requirements are
expressly stated so that they can be proved.

One annoying bug in the PIC32MX processors is that instructions that
perform writes will sometimes do the write twice when interrupted - once
before the interrupt occurs, and once after it returns. Microchip
suggest that this is only a problem with certain peripherals, but it
seems to me that program code could be sensitive to this behaviour, and
consequently that it might cause a program failure.

The requirement is that each write operation is performed exactly once,
but how sure are we that that anyone would think to include it, absent
this bug mentioned in the errata.

Sylvia.

Marko Rauhamaa
Guest

Wed Jan 11, 2017 7:01 pm   



David Brown <david.brown_at_hesbynett.no>:

Quote:
On 11/01/17 11:23, Marko Rauhamaa wrote:
Now, automated proof checking *is* awe-inspiring: <URL:
http://us.metamath.org/mpeuni/fta.html>. No steps are skipped. For
example, proving "2 + 2 = 4" involves 2,452 subtheorems: <URL:
http://us.metamath.org/mpeuni/mmset.html#trivia>. And look at this
gem: <URL: http://us.metamath.org/mpeuni/dfbi1gb.html>!

That all depends on the kind of proofs you are looking for, what
definitions you are using, what axioms you are using, and so on. In
particular, this example is using complex numbers - the proof of 2 + 2 =
4 in natural numbers is far simpler. The example is also used to write
things in the way that generates the most impressive numbers, with every
sub-theorem expanded fully at every step, rather than the way proofs are
/really/ done by proving each sub-theorem only once.


No, Metamath doesn't expand subtheorems fully. It refers to them by
name.

The way proofs are ordinarily done, though, at least in all student
textbooks, is by doing a lot of hand-waving and expecting the reader to
connect the dots. Metamath connects all the dots for you.


Marko

Chris Jones
Guest

Wed Jan 11, 2017 8:24 pm   



On 11/01/2017 22:37, Sylvia Else wrote:
Quote:
On 11/01/2017 7:59 PM, David Brown wrote:
On 11/01/17 01:49, Sylvia Else wrote:
As I tear my hair out dealing with errata on the chips I'm using, I find
myself wondering what is the most complicated chip that's been designed
that was error free from the time it was first release to the market?

Sylvia.

When the Inmos "transputer" chip was designed (I don't remember which
particular chip), the design was independently checked by a formal
mathematical proof done by a university team, and by exhaustive checking
of every combination for all instructions (using large numbers of chips
running in parallel for half a year or so).

The two checks found exactly the same set of errors, which were then
corrected.


Of course, there might have been problems or errata on issues other than
the logical operation of the cpu.


Even with proofs, you need to be sure that all the requirements are
expressly stated so that they can be proved.

One annoying bug in the PIC32MX processors is that instructions that
perform writes will sometimes do the write twice when interrupted - once
before the interrupt occurs, and once after it returns. Microchip
suggest that this is only a problem with certain peripherals, but it
seems to me that program code could be sensitive to this behaviour, and
consequently that it might cause a program failure.

The requirement is that each write operation is performed exactly once,
but how sure are we that that anyone would think to include it, absent
this bug mentioned in the errata.

Sylvia.


I'm not sure how entirely error-free it was, but the first ARM processor
worked first time:
https://youtu.be/D4nWLIeBuf4?t=302
https://youtu.be/_a9OoExi-Rc?t=198

The thing that bothers me about Microchip's errata is that some bugs
stay unchanged in the errata even when they have seemingly done at least
one all-layer tape-out after they knew about the bug. In my opinion, any
fault that they are not going to even *try* to fix in an all-layer
tape-out should be described fully and honestly in the datasheet rather
than being hidden in the errata, otherwise it borders on false
advertising. Write endurance of the EEPROM being much lower than the
datasheet says is one of the "bugs" that I am thinking about.

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