valtih1978
Guest
Sat Jul 30, 2011 10:03 am
entity SPY is
port (A : inout Std_Logic);
end SPY;
architecture ARCH of SPY is
begin
process begin
report time'image(now) & ": a = " & std_logic'image(a);
wait on a'transaction;
end process;
end architecture;
architecture TB is
signal A: std_logic;
begin
SPY_I: entity SPY(a)
process begin
wait for 1 fs;
a <= 'Z'; wait for 1 ps;
a <= '1'; wait for 5 ns;
a <= '0'; wait for 20 ns;
end process
I do not drive the signal from the Spy, so output must be (U, Z, 1, 0).
Right? Yet, simulator tells 'a = U' all four times!
I observed this hacking the Zero-Ohm model. Ben Cohen temporarly assigns
a and b to Z there. I do not understand why but that is a solution to
get the normal output (U,Z,1,0). Another is to change port type inout ->
in. Is is supposed VHDL behaviour? IMO, it is strange furthermore
because I consider normal, architecture-declared signals, as inout
because you can read and write them but no problem happens when the
monitoring process is located within the same architecture that drives
the signal rather than in a separate entity.
Guest
Sat Jul 30, 2011 5:49 pm
valtih1978 <do_at_not.email.me> wrote:
Quote:
entity SPY is
port (A : inout Std_Logic);
end SPY;
architecture ARCH of SPY is
begin
process begin
report time'image(now) & ": a = " & std_logic'image(a);
wait on a'transaction;
end process;
end architecture;
architecture TB is
signal A: std_logic;
begin
SPY_I: entity SPY(a)
process begin
wait for 1 fs;
a <= 'Z'; wait for 1 ps;
a <= '1'; wait for 5 ns;
a <= '0'; wait for 20 ns;
end process
I do not drive the signal from the Spy, so output must be (U, Z, 1, 0).
Right? Yet, simulator tells 'a = U' all four times!
Signal A in the Testbench TB has multiple sources[1]: spy's inout port
and the driver from the process in the testbench. The inout source from
spy is initialized with 'U' by default. That 'U' overdrives the other
assignments like usual.
If you initialize the inout port using 'Z', spy will report the values
assigned by the testbench process.
....
port (A: inout std_logic := 'Z');
....
[1]: LRM(93) 4.3.1.2 line 183
Enrik
