$monitor and icarus (iverilog)

Wed Feb 09, 2011 11:34 pm   

Newbie Alert. Learning verilog with gEDA tools - icarus

I am trying to implement a traffic light controller. Nothing complicated
here but I thought Id use system functions to simulate it ($monitor,
$display).

Compiles correctly with
iverilog -s top traffic_light.v

I run it with
vvp a.out and it produces the following:

TrafficLights=x
0 rst=1 clk=0 sw= 4 leds=X
TrafficLights=6
5 rst=1 clk=1 sw= 4 leds=X
TrafficLights=5
10 rst=0 clk=0 sw= 4 leds=X
TrafficLights=6
15 rst=1 clk=1 sw= 4 leds=X
20 rst=1 clk=0 sw= 4 leds=X
TrafficLights=5
25 rst=1 clk=1 sw= 4 leds=X
30 rst=1 clk=0 sw= 4 leds=X
TrafficLights=3
35 rst=1 clk=1 sw= 4 leds=X
40 rst=1 clk=0 sw= 4 leds=X
TrafficLights=6
45 rst=1 clk=1 sw= 4 leds=X
50 rst=1 clk=0 sw= 4 leds=X
TrafficLights=5
55 rst=1 clk=1 sw= 4 leds=X
60 rst=1 clk=0 sw= 4 leds=X
TrafficLights=3
65 rst=1 clk=1 sw= 4 leds=X
70 rst=1 clk=0 sw= 4 leds=X
TrafficLights=6
75 rst=1 clk=1 sw= 4 leds=X
80 rst=1 clk=0 sw= 4 leds=X
TrafficLights=5
85 rst=1 clk=1 sw= 4 leds=X
90 rst=1 clk=0 sw= 4 leds=X
TrafficLights=3
95 rst=1 clk=1 sw= 4 leds=X
100 rst=1 clk=0 sw= 4 leds=X



internal to the module the variable changes as expected, why isnt
this represented in the $monitor function' output in module top?

what am I not understanding?
Thanks



/*
************************************************************************
*name: traffic_light.v
*author: Samuel Igwe
*date: 2/8/2011 A.D
*description: verilog code to allow the xilinx xc95108 cpld board I put
* together to function like a traffic light indicator
************************************************************************
*/
module top;
reg SymClk=0,SymRst=1;
wire [3:0] SymSwitch=4;
wire [2:0] SymLeds=0;

traffic_light symtraffic (SymRst,SymClk,SymSwitch,SymLeds);

initial
$monitor("%d\trst=%d\tclk=%d\tsw=%d\tleds=%d",
$time,SymRst,SymClk,SymSwitch,SymLeds);

always
begin
#5 SymClk <= ~SymClk;
if ($time == 10)
SymRst <=0;
else
SymRst <=1;

if ($time == 100)
$finish;

end
endmodule


module traffic_light(input InRstSw,
input InClock,
input [3:0] InMouseSw,
output reg [2:0] TrafficLights);

parameter RED =3'b110;
parameter YELLOW=3'b101;
parameter GREEN =3'b011;

reg [2:0] RYG_LED;

initial
RYG_LED <= RED;


always @ (RYG_LED)
begin
TrafficLights <= RYG_LED;
$display("TrafficLights=%x",TrafficLights);
end


always @ (posedge InClock or negedge InRstSw)
begin
if(InClock)
begin
case(RYG_LED)
RED:
RYG_LED <= YELLOW;
YELLOW:
RYG_LED <= GREEN;
GREEN:
RYG_LED <= RED;
default:
RYG_LED <= YELLOW;
endcase
end
else
RYG_LED <= RED;
end
endmodule

Thu Feb 10, 2011 12:50 am   

On 2/9/2011 2:34 PM, Aldorus wrote:


You are assigning to the net SymLeds in two places and there is
contention between these two assignments. At the top level you have an
implicit continuous assignment with a value of 0 in the definition and
the output of the module instantiation also creates an implicit
continuous assignment. FYI using %b instead of %d shows exactly which
bits are in contention. Removing the assignment to zero in the
definition should make things work as expected.

Cary

Thu Feb 10, 2011 1:29 am   

On Wed, 09 Feb 2011 15:50:41 -0800, Cary R. wrote:


That worked

Odd thing is the only reason I set it to 0 was to have it initialized for
simulation purposes - thats not sensible since I had a SymRst in play to
set defaults.

Thanks again