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m
Guest

Fri Mar 11, 2005 10:02 pm   



Hi,
Currently I have a design which has many 32 bit multipliers and 64 bit
adders and the area results are discouraging. The nice thing is that I
have a lot of cycles to implement this algorithm. One solution is to
use a few instantiated MACs and mux all the inputs/outputs over many
cycles. Of course this is a tedious and error-prone process. The
question is if I had a Module Compiler license, can I recode this
Verilog implementation in MC language and get MC to do this for me
automatically. If yes, how difficult would it the conversion be ?

Any suggestions, ideas are welcome.

Thanks.

P Ruetz
Guest

Mon Mar 14, 2005 1:27 am   



"mk" <kal*@dspia.*comdelete> wrote in message
news:1s4431dbvhl7fmlrhlgopv9mbd7epn58ku_at_4ax.com...
Quote:
Hi,
Currently I have a design which has many 32 bit multipliers and 64 bit
adders and the area results are discouraging. The nice thing is that I
have a lot of cycles to implement this algorithm. One solution is to
use a few instantiated MACs and mux all the inputs/outputs over many
cycles. Of course this is a tedious and error-prone process. The
question is if I had a Module Compiler license, can I recode this
Verilog implementation in MC language and get MC to do this for me
automatically. If yes, how difficult would it the conversion be ?

Any suggestions, ideas are welcome.

Thanks.


I have not had any connection to MC for some time now, but I was one of the
original developers. If I understand your question, you are wondering if MC
will automatically make serial-parallel tradeoffs when the clock rate is
higher than the data rate. As far as I know, MC does not do this. It will
allow you to play with these tradeoffs (you have to code the architecture)
to determine which you want to use. This may not sound like much, but the
MC language is fairly adept at describing parameterized architectures (i.e.
you have a parameter n that indicates the number of cycles you want to reuse
each multiplier and hence your design would need N/n multiplier where N is
the number of multiplications required). If your multiplications are highly
related and regular (e.g. an inner product or FIR filter), then this
approach makes a lot of sense and MC can do more for you. If not, you might
just end up designing something that looks more like a CPU and MC will be
less useful.

FYI, BC (Behavioral compiler) from Synopsys was designed to do exactly what
you want, but was a less than stellar success and pulled from the market
years ago. I think the problem was that designers could do a better job
manually, but I had no involvement with this product.

You could also ask this question on ESNUG as there might be some MC users
there to help you.

Hope this helps at least a little,
Peter

Alvin Andries
Guest

Wed Jun 15, 2005 6:43 pm   



"mk" <kal*@dspia.*comdelete> wrote in message
news:1s4431dbvhl7fmlrhlgopv9mbd7epn58ku_at_4ax.com...
Quote:
Hi,
Currently I have a design which has many 32 bit multipliers and 64 bit
adders and the area results are discouraging. The nice thing is that I
have a lot of cycles to implement this algorithm. One solution is to
use a few instantiated MACs and mux all the inputs/outputs over many
cycles. Of course this is a tedious and error-prone process. The
question is if I had a Module Compiler license, can I recode this
Verilog implementation in MC language and get MC to do this for me
automatically. If yes, how difficult would it the conversion be ?

Any suggestions, ideas are welcome.

Thanks.

Hi,

Isn't there a sequential multiplier in DW (assuming that youo have a
license) included?

Regards,
Alvin Andries.

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