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Minimum time execution for APB operation.

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MJ
Guest

Fri Dec 07, 2018 10:45 am   



Hello guys,

I have one doubt regarding FSM modeling.
In the APB specification, it is given that the minimum no. of cycles required for the completion is two cycles. However, if you model acc. to the FSM given in the spec, it will take three cycles i.e., using three states(IDLE, SETUP , ACCESS).

since we write State memory as

always@(posedge clk)
begin
if(reset)
state <= IDLE;
else
state <= nextstate;
end

For ex if it is in the IDLE state once PSEL,PWRITE and PADDR are asserted in the same cycle it wont change the state right. It will change to SETUP state in the next clock cycle and in SETUP after PENABLE goes to 1 in the next cycle it will go to ACCESS.

My question is in the above duration it will takes three clock cycles to complete the operation from assertion of PSEL,PWRITE,PADDR.
Then how it will have minimum two clock cycle for the completion of operation?

Also, whenever Penable is asserted it wont enter into ACCESs phase in the same clock cycle, the transistion bw two states requires one clock cycle right?

Please, anyone clear my doubt.

Richard Damon
Guest

Fri Dec 07, 2018 12:45 pm   



On 12/7/18 4:15 AM, MJ wrote:
Quote:
Hello guys,

I have one doubt regarding FSM modeling.
In the APB specification, it is given that the minimum no. of cycles required for the completion is two cycles. However, if you model acc. to the FSM given in the spec, it will take three cycles i.e., using three states(IDLE, SETUP , ACCESS).

since we write State memory as

always@(posedge clk)
begin
if(reset)
state <= IDLE;
else
state <= nextstate;
end

For ex if it is in the IDLE state once PSEL,PWRITE and PADDR are asserted in the same cycle it wont change the state right. It will change to SETUP state in the next clock cycle and in SETUP after PENABLE goes to 1 in the next cycle it will go to ACCESS.

My question is in the above duration it will takes three clock cycles to complete the operation from assertion of PSEL,PWRITE,PADDR.
Then how it will have minimum two clock cycle for the completion of operation?

Also, whenever Penable is asserted it wont enter into ACCESs phase in the same clock cycle, the transistion bw two states requires one clock cycle right?

Please, anyone clear my doubt.


I don't have the spec in front of me at the moment, but my guess is that
ACCESS can go to SETUP if a new request is present in time, and then the
sequence is:

IDLE, SETUP, ACCESS, SETUP, ACCESS, ...

so back to back cycles only take 2 clock cycles each (the first takes 3).

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