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Migrating to Actel Libero

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matrix
Guest

Wed Nov 16, 2011 2:57 pm   



Hello all.
I am trying to migrate from Xilinx ISE to Actel Libero. I created a ne
project in Libero and copied the *.vhd files from the ISE project. Then
replaced all the Xilinx FIFOs and CLKDLLs with the equivalent Liber
specific cores. When I tried to synthesize the project using Synplify Pro
I obtained the following error message.
"Can't open input fil
C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd"
I am not using any Unisim components in the Actel Libero project. Then wha
cause can result in this error.

Thank you.



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Thomas Stanka
Guest

Wed Nov 16, 2011 5:47 pm   



On 16 Nov., 14:57, "matrix" <ravikrishnanunni_at_n_o_s_p_a_m.gmail.com>
wrote:
Quote:
C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd"
I am not using any Unisim components in the Actel Libero project. Then what
cause can result in this error.

Are you sure that you have no usage of library unisim in any file? Try
searching for "library unisim" in all hdl files.
I guess that Synplify has some build in mechanismes to check under
<libpath>/xilinx if unisim or simprim is used in design. But actually
I'm surprised that even the Actelversion of Synplify has this build
in.

bye Thomas

Brian Drummond
Guest

Thu Nov 17, 2011 1:06 am   



On Wed, 16 Nov 2011 07:57:19 -0600, matrix wrote:

Quote:
Hello all.
I obtained the following error message. "Can't open input file
C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd"
I am not using any Unisim components in the Actel Libero project. Then
what cause can result in this error.

You may have replaced any such components, but it is possible that some
source files still contain (now unnecessary) library clauses, referencing
the unisim library.

- Brian

matrix
Guest

Fri Nov 18, 2011 10:15 am   



Quote:
On Wed, 16 Nov 2011 07:57:19 -0600, matrix wrote:

Hello all.
I obtained the following error message. "Can't open input file

C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd"
I am not using any Unisim components in the Actel Libero project. Then
what cause can result in this error.

You may have replaced any such components, but it is possible that some
source files still contain (now unnecessary) library clauses, referencin

the unisim library.

- Brian

Solved. One of the source files contained a library initialization fo

unisim, as Thomas and Brian had pointed out. Removed that clause and th
error message disappeared.
Thank you all.

---------------------------------------
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elektroda.net NewsGroups Forum Index - FPGA - Migrating to Actel Libero

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