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median filter with verilog ?

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Guest

Mon Aug 20, 2018 6:45 pm   



Someone has an idea how to do it ?

Michael Kellett
Guest

Tue Aug 21, 2018 9:45 am   



On 20/08/2018 18:23, danielshalom431_at_gmail.com wrote:
Quote:
Someone has an idea how to do it ?

Is your problem with writing the Verilog, understanding the process or
using Google ?

There is a Wiki article that explains the basics and Google can find the
OpenCores project written in Verilog.

Why not define what you want to do, have a go at it and then come back
and ask questions ?

MK

Y.V.V.Nagendra
Guest

Tue Aug 21, 2018 6:45 pm   



On Monday, August 20, 2018 at 10:53:11 PM UTC+5:30, daniels...@gmail.com wrote:
> Someone has an idea how to do it ?

It seems you forget attaching the "it"!

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