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LVS. Probe av_extracted nets.

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elektroda.net NewsGroups Forum Index - Cadence - LVS. Probe av_extracted nets.

JM2000
Guest

Fri May 31, 2019 6:45 pm   



Hi,

I have configured the LVS schematic view with symbols to measure the performance of my layout and schematic. The layout is type av_extracted.

I have a question regarding measuring nodes within the extracted view that are not connected to any pins (I/O).

For example, I have a two stage LNA and I do not have a pin connection between the stages. I would like to probe this connection or net to measure the AC signal and ensure the correct DC voltage is placed across the node.

How exactly do I probe extracted nets?

Yuan Mo
Guest

Sat Jun 01, 2019 2:45 pm   



On Saturday, June 1, 2019 at 1:38:29 AM UTC+8, JM2000 wrote:
Quote:
Hi,

I have configured the LVS schematic view with symbols to measure the performance of my layout and schematic. The layout is type av_extracted.

I have a question regarding measuring nodes within the extracted view that are not connected to any pins (I/O).

For example, I have a two stage LNA and I do not have a pin connection between the stages. I would like to probe this connection or net to measure the AC signal and ensure the correct DC voltage is placed across the node.

How exactly do I probe extracted nets?


Put a pin on the net you interested, then you can probe the signal after postlayout simulation. Otherwise I don't think there will be a better way to do this.

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