kris
Guest
Tue Oct 19, 2004 2:33 am
Does someone know of a tool that finds the combinatorial logic that is
affected by a set of registers and input
ports?
In the EDA community they call this a logic cone (Logic cones are groups
of logic bordered by registers, ports or black boxes.) It is a.o. used in
verification tools.
In my case I do not want to compare two design as in a logic equivalence
check. I would simply like a netlist of cells.
Kris
Chris Alexander
Guest
Tue Oct 19, 2004 7:44 pm
I wrote a tool that does what you're asking about some years ago. It
takes verilog gate netlists and traces signal sources backward/forward
to registers or I/O.
There are some technology specific elements - I seem to recall putting
together a libraries for Xilinx, NEC and LSI gate arrays.
Send me some mail if you are interested.
Chris
"kris" <twofold_at_gmx.net> wrote in message news:<cl1uc9$ebk$1_at_daisy.noc.ucla.edu>...
Quote:
Does someone know of a tool that finds the combinatorial logic that is
affected by a set of registers and input
ports?
In the EDA community they call this a logic cone (Logic cones are groups
of logic bordered by registers, ports or black boxes.) It is a.o. used in
verification tools.
In my case I do not want to compare two design as in a logic equivalence
check. I would simply like a netlist of cells.
Kris
