hssig
Guest
Mon Sep 12, 2011 9:46 am
Hi,
I want to use VHDL-2008 generic packages so that I can pass a generic
to the package from the generic
of a component (in which the package is used), I read about "local
packages" in VHDL-2008, but the problem with them is that I need the
package instantiation after the generic part and before the
port declaration of the component. But this is not the declarative
part of an entity. Is that kind of generic structure possible at all
in VHDL-2008?
library ieee;
use ieee.std_logic_1164.all;
package pkg_test is
generic( NUM : positive :=77);
type t_type is array(0 to NUM) of std_logic_vector(NUM downto 0);
end package;
library ieee;
use ieee.std_logic_1164.all;
entity test_component is
generic( NUM_TEST : positive := 4 );
-- THIS is NOT the declarative part of an entity
library work;
use work.pkg_test.all;
package pkg_test_inst is new work.pkg_test -- Local Package
2008 ????
generic map( NUM => NUM_TEST);
library work;
use work.pkg_test_inst.all;
port(
SigIn : in t_type;
SigOut : out t_type
);
-- THIS is the declarative part of an entity
end entity;
architecture test of test_component is
begin
SigOut <= SigIn;
end architecture;
hssig
Guest
Fri Oct 07, 2011 9:35 am
No response or suggestion yet.
From the Aldec newsletter:
"Do you know that the majority of hardware description languages
(including SystemVerilog) is developed by companies that purchased
IEEE-SA membership and individual users have no say in the process?
VHDL does not follow this trend, and the working group developing the
next version of the standard is looking for passionate individuals who
would like to spend some time improving the language. Everyone is
welcome and encouraged to visit
www.eda.org and help make a decision."
My post does show a generic construct which could be essential in our
FPGA designs if supported.
Cheers, hssig
HT-Lab
Guest
Fri Oct 07, 2011 10:57 am
On 07/10/2011 08:35, hssig wrote:
Quote:
No response or suggestion yet.
That is probably because not many of us can try your example. Modelsim
(which is what I use) currently only supports constant generics on
packages but I understand the second 10.1 beta release should expand on
this. Reading the LRM is just too painful...;-)
Hans
www.ht-lab.com
Quote:
From the Aldec newsletter:
"Do you know that the majority of hardware description languages
(including SystemVerilog) is developed by companies that purchased
IEEE-SA membership and individual users have no say in the process?
VHDL does not follow this trend, and the working group developing the
next version of the standard is looking for passionate individuals who
would like to spend some time improving the language. Everyone is
welcome and encouraged to visit
www.eda.org and help make a decision."
My post does show a generic construct which could be essential in our
FPGA designs if supported.
Cheers, hssig
hssig
Guest
Mon Oct 10, 2011 1:58 pm
Quote:
the second 10.1 beta release
Yes, I will participate in the second phase of Modeslim 10.1 beta
program. We will see ...
Cheers, hssig
hssig
Guest
Wed Oct 12, 2011 10:10 am
First try with Modelsim Pe 10.1beta2
vcom -2008 test_compnent.vhd
# Model Technology ModelSim PE vcom 10.1 Beta 2 Compiler 2011.10 Oct
1 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package pkg_test
# -- Compiling entity test_component
# ** Error: test_compnent.vhd(15): near "library": syntax error
# -- Loading package pkg_test
# ** Error: test_compnent.vhd(16): A member of an uninstantiated
package is referenced outside the scope of the package.
# ** Error: test_compnent.vhd(17): VHDL Compiler exiting
# C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed.
Cheers,
hssig
HT-Lab
Guest
Mon Oct 17, 2011 8:49 am
On 12/10/2011 09:10, hssig wrote:
Quote:
First try with Modelsim Pe 10.1beta2
...
# ** Error: test_compnent.vhd(16): A member of an uninstantiated
package is referenced outside the scope of the package.
# ** Error: test_compnent.vhd(17): VHDL Compiler exiting
# C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed.
Cheers,
hssig
Hi Hssig,
I found the same, apparently full generics including type generics will
not be supported until 10.2.
Does anybody know if Aldec supports type generics? (see modified Doulos
example below).
Hans
www.ht-lab.com
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std_unsigned.all;
entity incrementer is
generic (type data_type);
port (I : in data_type;
O : out data_type;
inc : in boolean);
end entity incrementer;
architecture RTL of incrementer is
begin
O <= I + '1' when inc = true;
end architecture RTL;
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (I : in std_logic_vector(7 downto 0);
O : out std_logic_vector(7 downto 0));
end entity top;
architecture RTL of top is
begin
incr_inst : entity work.incrementer
generic map ( data_type => std_logic_vector(7 downto 0),
increment => true )
port map ( I => I, O => O, inc => true );
end architecture RTL;
Matthias Alles
Guest
Mon Oct 17, 2011 1:21 pm
Hi Hans,
a quick try with RivieraPro 2011.06 gives:
COMP96 ERROR COMP96_0666: "Declaring interface types that appear as
generics in design entities, components, blocks, or subprograms is not
supported yet. Please contact Aldec Support to receive the latest
status." "test.vhd" 6 12
For the upcoming 2011.10 release they promise the support of new VHDL
constructs. Maybe this one will be supported then.
Best regards,
Matthias
Am 17.10.2011 10:49, schrieb HT-Lab:
Quote:
On 12/10/2011 09:10, hssig wrote:
First try with Modelsim Pe 10.1beta2
..
# ** Error: test_compnent.vhd(16): A member of an uninstantiated
package is referenced outside the scope of the package.
# ** Error: test_compnent.vhd(17): VHDL Compiler exiting
# C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed.
Cheers,
hssig
Hi Hssig,
I found the same, apparently full generics including type generics will
not be supported until 10.2.
Does anybody know if Aldec supports type generics? (see modified Doulos
example below).
Hans
www.ht-lab.com
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std_unsigned.all;
entity incrementer is
generic (type data_type);
port (I : in data_type;
O : out data_type;
inc : in boolean);
end entity incrementer;
architecture RTL of incrementer is
begin
O <= I + '1' when inc = true;
end architecture RTL;
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (I : in std_logic_vector(7 downto 0);
O : out std_logic_vector(7 downto 0));
end entity top;
architecture RTL of top is
begin
incr_inst : entity work.incrementer
generic map ( data_type => std_logic_vector(7 downto 0),
increment => true )
port map ( I => I, O => O, inc => true );
end architecture RTL;
HT-Lab
Guest
Mon Oct 17, 2011 3:52 pm
Hi Matthias,
Thanks for trying it out. It looks like Mentor is not that far behind.
Regards,
Hans.
www.ht-lab.com
On 17/10/2011 14:21, Matthias Alles wrote:
Quote:
Hi Hans,
a quick try with RivieraPro 2011.06 gives:
COMP96 ERROR COMP96_0666: "Declaring interface types that appear as
generics in design entities, components, blocks, or subprograms is not
supported yet. Please contact Aldec Support to receive the latest
status." "test.vhd" 6 12
For the upcoming 2011.10 release they promise the support of new VHDL
constructs. Maybe this one will be supported then.
Best regards,
Matthias
Am 17.10.2011 10:49, schrieb HT-Lab:
On 12/10/2011 09:10, hssig wrote:
First try with Modelsim Pe 10.1beta2
..
# ** Error: test_compnent.vhd(16): A member of an uninstantiated
package is referenced outside the scope of the package.
# ** Error: test_compnent.vhd(17): VHDL Compiler exiting
# C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed.
Cheers,
hssig
Hi Hssig,
I found the same, apparently full generics including type generics will
not be supported until 10.2.
Does anybody know if Aldec supports type generics? (see modified Doulos
example below).
Hans
www.ht-lab.com
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std_unsigned.all;
entity incrementer is
generic (type data_type);
port (I : in data_type;
O : out data_type;
inc : in boolean);
end entity incrementer;
architecture RTL of incrementer is
begin
O<= I + '1' when inc = true;
end architecture RTL;
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (I : in std_logic_vector(7 downto 0);
O : out std_logic_vector(7 downto 0));
end entity top;
architecture RTL of top is
begin
incr_inst : entity work.incrementer
generic map ( data_type => std_logic_vector(7 downto 0),
increment => true )
port map ( I => I, O => O, inc => true );
end architecture RTL;
JimLewis
Guest
Tue Oct 18, 2011 1:46 am
Hi Hssig,
It looks to me like the structure of your entity is incorrect.
Structure of the entity is:
entity identifier is
entity_header
entity_declarative_part
[ begin
entity_statement_part ]
end [ entity ] [ entity_simple_name ] ;
Local package declarations go in the entity_declarative_part.
OTOH, generic and port clauses go in the entity_header.
VHDL-2008 has another feature that will solve your problem
in a easier fashion. Composites can now have unconstrained
elements. As a result you can declare:
type t_type is array(integer range <>) of std_logic_vector;
then use it as:
signal A : t_type(0 to NUM)(NUM downto 0) ;
Good luck,
Jim
