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Guest

Fri Aug 04, 2017 8:13 am   



I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim.

library ieee;
use ieee.std_logic_1164.all;

--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;

architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed
signal temp_done : std_logic;

begin

process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';

elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;


rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto Cool;
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`

The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement.

And the testbench I used is this:

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_tb is
end lfsr_tb;

architecture test_bench of lfsr_tb is

component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );

end component;


signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;

signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;

begin

mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );

clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;

reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;

end test_bench;

I cannot understand what is wrong in the code.
Kindly guide as its related to my project.

rickman
Guest

Fri Aug 04, 2017 5:48 pm   



hamzar105_at_gmail.com wrote on 8/4/2017 2:13 AM:
Quote:
I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim.

library ieee;
use ieee.std_logic_1164.all;

--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;

architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed
signal temp_done : std_logic;

begin

process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';

elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;


rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto Cool;
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`

The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement.

And the testbench I used is this:

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_tb is
end lfsr_tb;

architecture test_bench of lfsr_tb is

component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );

end component;


signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;

signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;

begin

mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );

clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;

reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;

end test_bench;

I cannot understand what is wrong in the code.
Kindly guide as its related to my project.


Try taking a look at your reset and enable signals. See if they are doing
what you expect.

--

Rick C

Evgeny Filatov
Guest

Fri Aug 04, 2017 8:17 pm   



On 04.08.2017 9:13, hamzar105_at_gmail.com wrote:
Quote:
I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim.

library ieee;
use ieee.std_logic_1164.all;

--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;

architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed
signal temp_done : std_logic;

begin

process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';

elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;


rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto Cool;
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`

The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement.

And the testbench I used is this:

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_tb is
end lfsr_tb;

architecture test_bench of lfsr_tb is

component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );

end component;


signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;

signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;

begin

mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );

clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;

reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;

end test_bench;

I cannot understand what is wrong in the code.
Kindly guide as its related to my project.


Why do you think this particular shift register would generate random
values?

If you have just connected some random taps and expect it to produce a
long sequence, you couldn't be more wrong.

These sorts of things should be designed, before you implement anything
in VHDL.

Gene

rickman
Guest

Sat Aug 05, 2017 12:45 am   



Evgeny Filatov wrote on 8/4/2017 2:17 PM:
Quote:
On 04.08.2017 9:13, hamzar105_at_gmail.com wrote:
I am new to VHDL, but have some idea. I made this LFSR but don't know why
it is stuck between the initial seed value and the other XOR value. I am
working with Altera Quartus 16 Lite and ISim.

library ieee;
use ieee.std_logic_1164.all;

--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;

architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1'
,others => '0'); --initial value as seed
signal temp_done : std_logic;

begin

process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';

elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor
temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) &
temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor
temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11
downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;


rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto Cool;
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`

The commented out temp_out is actual feedback (taps are 16,15,13, and 4)
as I checked with random taps but still no improvement.

And the testbench I used is this:

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_tb is
end lfsr_tb;

architecture test_bench of lfsr_tb is

component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );

end component;


signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;

signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;

begin

mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );

clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;

reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;

end test_bench;

I cannot understand what is wrong in the code.
Kindly guide as its related to my project.


Why do you think this particular shift register would generate random values?

If you have just connected some random taps and expect it to produce a long
sequence, you couldn't be more wrong.

These sorts of things should be designed, before you implement anything in
VHDL.


There is also the issue of a shift register needing to be shifted to call it
a shift register.

--

Rick C

Mark Curry
Guest

Sat Aug 05, 2017 1:00 am   



In article <om2t73$94t$1_at_dont-email.me>, rickman <gnuarm_at_gmail.com> wrote:
Quote:
Evgeny Filatov wrote on 8/4/2017 2:17 PM:
On 04.08.2017 9:13, hamzar105_at_gmail.com wrote:
I am new to VHDL, but have some idea. I made this LFSR but don't know why
it is stuck between the initial seed value and the other XOR value. I am
working with Altera Quartus 16 Lite and ISim.

library ieee;
use ieee.std_logic_1164.all;

--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;

architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1'
,others => '0'); --initial value as seed
signal temp_done : std_logic;

begin

process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';

elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor
temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) &
temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor
temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11
downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;


rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto Cool;
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`

The commented out temp_out is actual feedback (taps are 16,15,13, and 4)
as I checked with random taps but still no improvement.

And the testbench I used is this:

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_tb is
end lfsr_tb;

architecture test_bench of lfsr_tb is

component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );

end component;


signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;

signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;

begin

mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );

clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;

reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;

end test_bench;

I cannot understand what is wrong in the code.
Kindly guide as its related to my project.


Why do you think this particular shift register would generate random values?

If you have just connected some random taps and expect it to produce a long
sequence, you couldn't be more wrong.

These sorts of things should be designed, before you implement anything in
VHDL.

There is also the issue of a shift register needing to be shifted to call it
a shift register.


Also, it looks like OP is initializing the shift registers to all zeros (My VHDL poor).
All-zeros LFSRs are usually degenerate-cases which are "stuck" at all zeros. (Primitive
polynomial LFSRs have periods of 2^N - 1. Where "N" is the number of bits. The degenerate
last state (usually all zeros) wraps around to itself.

Regards,

Mark

rickman
Guest

Sat Aug 05, 2017 2:31 am   



Mark Curry wrote on 8/4/2017 7:00 PM:
Quote:
In article <om2t73$94t$1_at_dont-email.me>, rickman <gnuarm_at_gmail.com> wrote:
Evgeny Filatov wrote on 8/4/2017 2:17 PM:
On 04.08.2017 9:13, hamzar105_at_gmail.com wrote:
I am new to VHDL, but have some idea. I made this LFSR but don't know why
it is stuck between the initial seed value and the other XOR value. I am
working with Altera Quartus 16 Lite and ISim.

library ieee;
use ieee.std_logic_1164.all;

--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;

architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1'
,others => '0'); --initial value as seed
signal temp_done : std_logic;

begin

process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';

elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor
temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) &
temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor
temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11
downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;


rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto Cool;
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`

The commented out temp_out is actual feedback (taps are 16,15,13, and 4)
as I checked with random taps but still no improvement.

And the testbench I used is this:

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_tb is
end lfsr_tb;

architecture test_bench of lfsr_tb is

component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );

end component;


signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;

signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;

begin

mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );

clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;

reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;

end test_bench;

I cannot understand what is wrong in the code.
Kindly guide as its related to my project.


Why do you think this particular shift register would generate random values?

If you have just connected some random taps and expect it to produce a long
sequence, you couldn't be more wrong.

These sorts of things should be designed, before you implement anything in
VHDL.

There is also the issue of a shift register needing to be shifted to call it
a shift register.

Also, it looks like OP is initializing the shift registers to all zeros (My VHDL poor).
All-zeros LFSRs are usually degenerate-cases which are "stuck" at all zeros. (Primitive
polynomial LFSRs have periods of 2^N - 1. Where "N" is the number of bits. The degenerate
last state (usually all zeros) wraps around to itself.


You are correct that there is typically a degenerate state that does not
change. But the OP has avoided this trap.

if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');

This code sets the LS bit to a one and all others a zero.

It's been a while since I dug into LFSRs, but I believe there is a form
where the all ones state is degenerate, I can't recall exactly.

--

Rick C

Mark Curry
Guest

Mon Aug 07, 2017 6:45 pm   



In article <om33df$upn$1_at_dont-email.me>, rickman <gnuarm_at_gmail.com> wrote:
Quote:

You are correct that there is typically a degenerate state that does not
change. But the OP has avoided this trap.

if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');

This code sets the LS bit to a one and all others a zero.

It's been a while since I dug into LFSRs, but I believe there is a form
where the all ones state is degenerate, I can't recall exactly.


As I said - my VHDL is poor. I never understood that "others" syntax of VHDL.

Changing the LFSR feedback from XOR to XNOR will change the
degenerate state to all ones. With creative selection
of inversions, one could "pick" the degenerate state.

There's also a way to take a primitive polynomial LFSR,
and achieve the full 2^N period with a little trick (It
makes the LFSR non-linear, but that may be just academic...)

--Mark

rickman
Guest

Mon Aug 07, 2017 8:25 pm   



Mark Curry wrote on 8/7/2017 12:45 PM:
Quote:
In article <om33df$upn$1_at_dont-email.me>, rickman <gnuarm_at_gmail.com> wrote:

You are correct that there is typically a degenerate state that does not
change. But the OP has avoided this trap.

if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');

This code sets the LS bit to a one and all others a zero.

It's been a while since I dug into LFSRs, but I believe there is a form
where the all ones state is degenerate, I can't recall exactly.

As I said - my VHDL is poor. I never understood that "others" syntax of VHDL.


Yeah, I don't program in VHDL every day anymore so I forget a lot from one
job to the next and have to spend a few days relearning. I mostly go back
to my last job and look at my coding style from then.

Aggregate notation is not so hard really. There is the form where positions
are defined by the, well *position* of each field in the aggregate, e.g.
('1', '0', "00001") will become "1000001". Named association specifically
indicates the position of the assigned bits, e.g. (6 => '1', 5 downto 1 =>
"00000", 0 => '1'). The use of others to assign a default value requires it
to be the last association in the aggregate, e.g. (6 => '1', 0 => '1',
others => '0'). I don't believe named and positional association can be
mixed in an array. I've read they can be mixed across the items in a record.


Quote:
Changing the LFSR feedback from XOR to XNOR will change the
degenerate state to all ones. With creative selection
of inversions, one could "pick" the degenerate state.


Thanks.


Quote:
There's also a way to take a primitive polynomial LFSR,
and achieve the full 2^N period with a little trick (It
makes the LFSR non-linear, but that may be just academic...)


Yes, I believe it essentially requires detecting a certain state and
negating a bit to create the degenerate state. I've seen this in an FPGA
design.

--

Rick C

Mark Curry
Guest

Mon Aug 07, 2017 9:00 pm   



In article <omab3c$d8e$1_at_dont-email.me>, rickman <gnuarm_at_gmail.com> wrote:
Quote:
Mark Curry wrote on 8/7/2017 12:45 PM:
In article <om33df$upn$1_at_dont-email.me>, rickman <gnuarm_at_gmail.com> wrote:

You are correct that there is typically a degenerate state that does not
change. But the OP has avoided this trap.

if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');

This code sets the LS bit to a one and all others a zero.

It's been a while since I dug into LFSRs, but I believe there is a form
where the all ones state is degenerate, I can't recall exactly.

As I said - my VHDL is poor. I never understood that "others" syntax of VHDL.

Yeah, I don't program in VHDL every day anymore so I forget a lot from one
job to the next and have to spend a few days relearning. I mostly go back
to my last job and look at my coding style from then.

Aggregate notation is not so hard really. There is the form where positions
are defined by the, well *position* of each field in the aggregate, e.g.
('1', '0', "00001") will become "1000001". Named association specifically
indicates the position of the assigned bits, e.g. (6 => '1', 5 downto 1 =
"00000", 0 => '1'). The use of others to assign a default value requires it
to be the last association in the aggregate, e.g. (6 => '1', 0 => '1',
others => '0'). I don't believe named and positional association can be
mixed in an array. I've read they can be mixed across the items in a record.


Thanks Rick - I'd missed that the one argument in the assignment is
the index of the assigned to variable. Ok, it makes sense now, I guess.

Regards,

Mark

Thomas Stanka
Guest

Thu Aug 10, 2017 1:20 pm   



Am Freitag, 4. August 2017 08:13:24 UTC+2 schrieb hamz...@gmail.com:

> temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0);

This is no shift register. Temp_out(15 downto 11) will always be in resetvalue (all zero)
Shift would have been eg:

temp_out <= temp_out(14 downto 0) & Feeback;
or
temp_out <= Feedback & temp_out(15 downto 1);


Quote:
clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;


Are you serious with 20ps Clock periode?

Quote:
reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;


I doubt that this process is working as intended.

0 ps:
rst = 1
en = U
10 ps:
rst = 0
en = 1
800 ps:
rst = 1
en = 1
810 ps:
rst = 0
en = 1
1610 ps:
rst = 1
en = 1
1620 ps:
rst = 0
en = 1

bye Thomas

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