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kristoff
Guest

Tue Sep 27, 2016 12:54 am   



Hi all,


I am currently learning VHDL step by step, but I noticed there are also
quite a lot of projects written in verilog.

So, for somebody who knows the basis, what would be best?

- First get a very good knowledge of VHDL and then start with verilog

- or learn vhdl and verilog at the same time (as the two languages do
offer simular features).


Kristoff

Jan Coombs
Guest

Tue Sep 27, 2016 1:12 am   



On Mon, 26 Sep 2016 20:54:55 +0200
kristoff <kristoff_at_skypro.be> wrote:

Quote:
Hi all,


I am currently learning VHDL step by step, but I noticed there
are also quite a lot of projects written in verilog.

So, for somebody who knows the basis, what would be best?

- First get a very good knowledge of VHDL and then start with
verilog

- or learn vhdl and verilog at the same time (as the two
languages do offer simular features).


Probably only you will know whether you prefer to write every
thing in triplicate, or fall between the stepping stones.

Alternatively, if you model in MyHDL [1] it can export either, or
even both.

Jan Coombs
--
[1] myhdl.org

kristoff
Guest

Tue Sep 27, 2016 1:29 am   



Jan,



On 26-09-16 21:12, Jan Coombs wrote:
Quote:
I am currently learning VHDL step by step, but I noticed there
are also quite a lot of projects written in verilog.
So, for somebody who knows the basis, what would be best?
- First get a very good knowledge of VHDL and then start with
verilog
- or learn vhdl and verilog at the same time (as the two
languages do offer simular features).

Probably only you will know whether you prefer to write every
thing in triplicate, or fall between the stepping stones.


Well, my first interest is to understand the code written by others in
the many open-source projects out there.



Quote:
Alternatively, if you model in MyHDL [1] it can export either, or
even both.


Isn't it best first to learn (or at least to understand) the two "main"
languages and then move on to the alternatives?



Kristoff

rickman
Guest

Tue Sep 27, 2016 1:51 am   



On 9/26/2016 2:54 PM, kristoff wrote:
Quote:
Hi all,


I am currently learning VHDL step by step, but I noticed there are also
quite a lot of projects written in verilog.

So, for somebody who knows the basis, what would be best?

- First get a very good knowledge of VHDL and then start with verilog

- or learn vhdl and verilog at the same time (as the two languages do
offer simular features).


I have learned VHDL pretty well and have used Verilog some. I prefer
VHDL mainly because that is what I know well. Some have a quite strong
opinion that Verilog is much more productive and useful. I won't argue
about it until I learn Verilog better.

If you are going to learn both and have a good learning book for each of
these languages, here is one you might want to include.

HDL Chip Design, Douglas J. Smith

It has many more examples than other books and many show the same thing
in VHDL and Verilog. A great way to see the differences. I only wish I
had a copy that was updated for VHDL 2008. VHDL 2008 is a *huge*
improvement over previous versions. I will never go back to limiting
myself to older versions.

--

Rick C


Guest

Sun Oct 02, 2016 4:09 pm   



Quote:
Some have a quite strong
opinion that Verilog is much more productive and useful. I won't argue
about it until I learn Verilog better.


Simply speaking:
Verilog compiles every piece of code, VHDL compiles none...

VHDL does very strong type checking and also has a verbose syntax which is quite cumbersome, but at least, when the compiler does not complain, chances are high that the code does what the designer intended.

Two hints:
- Make use of some VHDL-2008 features (like process(all))
- Understand that you do not need component declarations, you can use
inst: entity work.foobar(rtl) port map (...)
without component statement.

Verilog will save you some time writing code but can result in extremely hard to find errors that turn out to be simply typos. At least a good editor is a must and I would suggest to read this: http://www.lcdm-eng.com/papers/snug06_Verilog%20Gotchas%20Part1.pdf

Can't comment on MyHDL and SystemVerilog...

Regards,

Thomas

www.entner-electronics.com - Home of EEBlaster and JPEG-Codec

Jan Coombs
Guest

Sun Oct 02, 2016 5:50 pm   



On Mon, 26 Sep 2016 21:29:21 +0200
kristoff <kristoff_at_skypro.be> wrote:
Quote:
On 26-09-16 21:12, Jan Coombs wrote:
Probably only you will know whether you prefer to write every
thing in triplicate, or fall between the stepping stones.

Well, my first interest is to understand the code written by
others in the many open-source projects out there.


I've done a lot of that, good for getting comfortable with RTL
and other novel aspects of hardware design. You did shake my
belief expressed in my intuitive comment above, so I checked a
project, and attached a summary below; the VHDL exported is
almost double the size of the verilog.

Quote:
Alternatively, if you model in MyHDL [1] it can export
either, or even both.

Isn't it best first to learn (or at least to understand) the
two "main" languages and then move on to the alternatives?


Its not like English vs Chinese! Whether you prefer the terse
or verbose, the underlying RTL is what you need to grok. My
preference is the less extreme choice, MyHDL.

MyHDL is a fast[2] free modelling tool, with substantial support
of Python libraries for design and test, and exports to waveform
viewer. Downside: you need good testing to prove design source
is valid and interpreted correctly[3]. Upside: you should be
doing this anyway!

As for writing Verilog/MyHDL/VHDL, use code templates, your own
or from net or tool manuals. Enjoy the trip, this low-level
stuff still fascinates me.

Jan Coombs
--
[1] myhdl.org
[2] http://old.myhdl.org/doku.php/performance
[3] http://docs.myhdl.org/en/stable/manual/unittest.html



# Sample_DesStruct.utxt

2014-11-08 jc Check imports, update to ...


Project source code tree:

kB LoC Idx
-- --- ---
7.0 170 1
1.9 50 1.1
5.1 116 1.2
5.2 139 1.3
6.9 180 1.3.1
10.0 265 1.4
4.1 60 1.4.1
2.2 90 1.4.2
4.3 102 1.5
5.3 156 1.5.1
1.6 60 1.4.1.1
1.5 60 1.5.1.2
17.0 436 1.5.2
2.3 90 1.5.2.1
14.1 333 1.5.3
6.7 161 1.5.3.1
9.7 246 1.5.4
---- ----
104.9 2794


Full Project Exports for Synthesis:

kB LoC
-- ---
94.1 2714 MyProj.v

173.9 2813 MyProj.vhd + 3k4B library


Notes:

Exported files contain block header comments only, the comment
sizes are identical:

kB LoC
-- ---
6.0 164 MyProj_NoCode.v
6.0 164 MyProj_NoCode.vhd

Source file code style is more compact than exports, and uses 2
space tabs, exports use 4 space tabs.


Hardware fabric after synthesis:

609 LUT4+FFs 3 RAMs

rickman
Guest

Mon Oct 03, 2016 7:30 am   



On 10/2/2016 10:09 AM, thomas.entner99_at_gmail.com wrote:
Quote:
Some have a quite strong opinion that Verilog is much more
productive and useful. I won't argue about it until I learn
Verilog better.

Simply speaking: Verilog compiles every piece of code, VHDL compiles
none...

VHDL does very strong type checking and also has a verbose syntax
which is quite cumbersome, but at least, when the compiler does not
complain, chances are high that the code does what the designer
intended.


Yes, that is the point of strong typing. It should eliminate the class
of errors that are due to mistakes in cross type assignments. This is
something that you have to understand very thoroughly in order to use
Verilog because it won't warn you, it will just do something that may or
may not be what you want.

This is where I am not sure which is preferable. I can write VHDL code
easily in spite of the "verboseness" of the language. I have yet to
even find a good book that tells you how to deal with these issues in
Verilog. I have asked about a good book to learn these issues from an
have been told in the Verilog group that there is none. Until I can
learn about this and be certain I am writing good code, I can't really
consider using Verilog professionally.


Quote:
Two hints: - Make use of some VHDL-2008 features (like process(all))
- Understand that you do not need component declarations, you can
use inst: entity work.foobar(rtl) port map (...) without component
statement.

Verilog will save you some time writing code but can result in
extremely hard to find errors that turn out to be simply typos. At
least a good editor is a must and I would suggest to read this:
http://www.lcdm-eng.com/papers/snug06_Verilog%20Gotchas%20Part1.pdf


Wow. This is a pretty long paper about "gotchas" in Verilog... 63
pages! I'm not sure I want to work with it.

--

Rick C

Tom Gardner
Guest

Mon Oct 03, 2016 2:16 pm   



On 03/10/16 04:05, rickman wrote:
Quote:
On 10/2/2016 10:09 AM, thomas.entner99_at_gmail.com wrote:
Verilog will save you some time writing code but can result in
extremely hard to find errors that turn out to be simply typos. At
least a good editor is a must and I would suggest to read this:
http://www.lcdm-eng.com/papers/snug06_Verilog%20Gotchas%20Part1.pdf

Wow. This is a pretty long paper about "gotchas" in Verilog... 63 pages! I'm
not sure I want to work with it.


How about C/C++? There are many discussions their
"characteristics"; I like the wryly amusing FQA
http://yosefk.com/c++fqa/

Having first used C in 1981 (gulp), I now feel uncomfortable
using it for anything more than a hack. Can you "cast away
constness" at the moment? I remember reading endless discussions
in the early 90s about whether it should be allowed or forbidden
in the standard.

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