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Latch/flip flip without the use of process

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Karl
Guest

Thu Nov 10, 2016 4:50 pm   



Hi,
I should have probably sent this question to the VHDL newsgrp but since it has low activity, I've decided to send it here.

It is well documented that processes should be used to code sequential systems. The texbook gives an example of a D latch/flip flip. With FPGA tools, i have to use a process so the tool makes use of the available on-chip flip flops. But i wonder what if I describe a D latch and flip flop without the use of process:
e.g.
1- latch: Q<=D when Clk='1'; (will this be triggered each time clk changes to 1 even if D does not change?)
2- flip flop: Q<=D when rising_edge(Clk); (the same question as above)

Is anything wrong with the above code?



Thank you

KJ
Guest

Thu Nov 10, 2016 5:49 pm   



On Thursday, November 10, 2016 at 9:50:38 AM UTC-5, Karl wrote:
Quote:
Hi,
I should have probably sent this question to the VHDL newsgrp but since it has low activity, I've decided to send it here.

It is well documented that processes should be used to code sequential systems. The texbook gives an example of a D latch/flip flip. With FPGA tools, i have to use a process so the tool makes use of the available on-chip flip flops. But i wonder what if I describe a D latch and flip flop without the use of process:
e.g.
1- latch: Q<=D when Clk='1'; (will this be triggered each time clk changes to 1 even if D does not change?)
2- flip flop: Q<=D when rising_edge(Clk); (the same question as above)


#1 will work as a latch; #2 will work as a flip flop. Both lines of code will be triggered upon any change on either D or Clk. But just because the code gets triggered and executed does not imply that Q gets updated. #1 will only update if Clk=1; #2 will only update when rising_edge(Clk) is true. At any other time there is no update to Q simply because there is no 'else ...' clause (which there shouldn't be for either a latch or flip flop).

Quote:
Is anything wrong with the above code?

The code is fine, your apparent desire to use a latch in an FPGA design will cause you problems if you implement.


Kevin Jennings

rickman
Guest

Fri Nov 11, 2016 12:54 am   



On 11/10/2016 9:50 AM, Karl wrote:
Quote:
Hi,
I should have probably sent this question to the VHDL newsgrp but since it has low activity, I've decided to send it here.

It is well documented that processes should be used to code sequential systems. The texbook gives an example of a D latch/flip flip. With FPGA tools, i have to use a process so the tool makes use of the available on-chip flip flops. But i wonder what if I describe a D latch and flip flop without the use of process:
e.g.
1- latch: Q<=D when Clk='1'; (will this be triggered each time clk changes to 1 even if D does not change?)
2- flip flop: Q<=D when rising_edge(Clk); (the same question as above)

Is anything wrong with the above code?


From what you wrote, the issue you fail to understand is that every
concurrent statement is a process. That is why they are concurrent,
each concurrent statement runs as a separate process. In fact, what
makes a process statement a process is that it is a concurrent
statement. What the process statement does is to tell the tool to stop
treating the following lines as processes, rather treat them as
sequential statements within the current process.

So why do you not want to use a process statement to define a FF?

To answer your question, as KJ wrote, each of your examples define a
type of register. When a signal level is used as the trigger it defines
a latch. When a signal edge is used as the trigger it defines an edge
sensitive FF. Seems rather obvious, no?

--

Rick C

Karl
Guest

Fri Nov 11, 2016 10:51 am   



Thank you KJ and Rickman for your answers. I wanted to confirm that the codes are correct because in the notes I am reading it stated that flip flops /latches are coded in VHDL using a process...given your answer, it is one way to do it but not the only one

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