Denisson
Guest
Wed Jun 16, 2010 2:30 am
Hi folks!
I'm trying to create in Verilog a interface to ready the keyboard
data. It's not really working well, and I request some advice :)
First of all, I'm trying to create a finite state machine. IDLE is the
state when CLOCK = 1 and DATA = 1 at the beggining. After the clock
goes down, the next state will be S0 and I read the OUTPUT (the START
BIT). The next state is S1 (the first data bit). The 11th bit is the
final one and after that the machine is set again in the IDLE state.
Is the idea correct?
Let's say I read the following sequence of bits: 0_00001011_01 I know
that the second and 9th bit is the scan code, but I didn't understand
how to convert this to ASCII.
Thanks for helping,
d_s_klein
Guest
Thu Jun 17, 2010 8:33 pm
On Jun 15, 5:00 pm, Denisson <denisso...@gmail.com> wrote:
Quote:
Hi folks!
I'm trying to create in Verilog a interface to ready the keyboard
data. It's not really working well, and I request some advice :)
First of all, I'm trying to create a finite state machine. IDLE is the
state when CLOCK = 1 and DATA = 1 at the beginning. After the clock
goes down, the next state will be S0 and I read the OUTPUT (the START
BIT). The next state is S1 (the first data bit). The 11th bit is the
final one and after that the machine is set again in the IDLE state.
Is the idea correct?
Let's say I read the following sequence of bits: 0_00001011_01 I know
that the second and 9th bit is the scan code, but I didn't understand
how to convert this to ASCII.
Thanks for helping,
One Google, two clicks:
<http://www.beyondlogic.org/keyboard/keybrd.htm>
Did you try a search before posting?
RK
