Keep model output delay value

Hi all,

I have a verilog model with specified output delay which is described
as following code. And I add a directive "`resetall" to prevent user
set
"`delay_mode_zero" at their top test-bench. But, the output delay was
disappear recently in other users' environment. And, I don't know why?

Any suggestion for keeping my model's output delay value without
affecting
by users' simulation options or settings ?

Thanks!

buf #0.35 I0 (rddata[0], rddata_tmp[0]);

On Fri, 22 Apr 2011 07:51:34 -0700 (PDT), Essen <essen...@gmail.com
wrote:

Hi all,

I have a verilog model with specified output delay which is described
as following code. And I add a directive "`resetall" to prevent user
set
"`delay_mode_zero" at their top test-bench. But, the output delay was
disappear recently in other users' environment. And, I don't know why?

Any suggestion for keeping my model's output delay value without
affecting
by users' simulation options or settings ?

Thanks!

buf #0.35 I0 (rddata[0], rddata_tmp[0]);

What's your `timescale setting?
--
Jonathan Bromley