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Java or Python parser for System Verilog testbench ?

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elektroda.net NewsGroups Forum Index - Verilog Language - Java or Python parser for System Verilog testbench ?

Bobby
Guest

Sun Sep 02, 2018 12:45 am   



I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

Questions:

(1) Considering my end goal, i.e. to generate SV TB,
a java parser would be better or python ?

(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in SV for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?



(3) Any technique to go on further with java parser ?


Looking forward for suggestions Smile

Johann Klammer
Guest

Sun Sep 02, 2018 4:45 pm   



On 09/02/2018 12:56 AM, Bobby wrote:
Quote:

I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

Questions:

(1) Considering my end goal, i.e. to generate SV TB,
a java parser would be better or python ?

(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in SV for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?



(3) Any technique to go on further with java parser ?


Looking forward for suggestions :-)






I believe pyparsing comes with a verilog parser in the examples directory.(verilogParse.py)

Petter Gustad
Guest

Wed Sep 05, 2018 9:45 pm   



Bobby <italienisch1987_at_gmail.com> writes:

Quote:
I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

Questions:

(1) Considering my end goal, i.e. to generate SV TB,
a java parser would be better or python ?


ANTLR4 is a pretty good parser generator. It supports both Java and
Python. I would say the parser generator and grammar specification
support is more important than your implementation language. Even though
the internals of ANTLR is written in Java.

//Petter


--
..sig removed by request.

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