EDAboard.com | EDAboard.de | EDAboard.co.uk | WTWH Media

ispLEVER - VHDL pin assignment

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - VHDL Language - ispLEVER - VHDL pin assignment

silverdr
Guest

Sun Mar 25, 2018 9:45 pm   



Hello everyone, I've encountered a problem with pin assignments in VHDL when using ispLEVER. Lattice has an answer to the generic question here:

http://www.latticesemi.com/en/Support/AnswerDatabase/1/8/4/1844

with link to a more thorough document in there. Both the answer and the document explain how to assign pins to given signals. They even give dummy examples there, like:

attribute LOC : string;
attribute LOC of out0: signal is "PA3";

The problem is that while this seems to work well with signals defined as e.. g. 'std_logic', when I try to use this for signals defined as 'std_logic_vector' and assign pins to f. e. address bus lines:

attribute LOC of A(1): signal is "P3";

things break and I get:

"design.vhd":19:20:19:20|Expecting : before class of object(s)" error. Workaround to this is to drop the vector definition and define each and every address line as a separate signal, but I would very much prefer to keep the vectors where they are. Does anyone know a way to assign pins to "vectored" signals?

silverdr
Guest

Mon Mar 26, 2018 4:45 pm   



OK - got the answer on another channel. Instead of

> attribute LOC of A(1): signal is "P3";

one needs to write:

attribute LOC of A: signal is "P4 P3 P2";

in other words for a signal defined as (f. e.)

A : out std_logic_vector(2 downto 0);

instead of giving the index and assigning one pin, to one signal of the "vector" I needed to give the whole "vector" and separate the pins by spaces in the value string.


Guest

Tue Mar 27, 2018 2:45 pm   



On Monday, 26 March 2018 17:19:37 UTC+2, silverdr wrote:
Quote:
OK - got the answer on another channel. Instead of

attribute LOC of A(1): signal is "P3";

one needs to write:

attribute LOC of A: signal is "P4 P3 P2";

in other words for a signal defined as (f. e.)

A : out std_logic_vector(2 downto 0);

instead of giving the index and assigning one pin, to one signal of the "vector" I needed to give the whole "vector" and separate the pins by spaces in the value string.


Thanks for posting the answer, too many don't do that

elektroda.net NewsGroups Forum Index - VHDL Language - ispLEVER - VHDL pin assignment

Ask a question - edaboard.com

Arabic version Bulgarian version Catalan version Czech version Danish version German version Greek version English version Spanish version Finnish version French version Hindi version Croatian version Indonesian version Italian version Hebrew version Japanese version Korean version Lithuanian version Latvian version Dutch version Norwegian version Polish version Portuguese version Romanian version Russian version Slovak version Slovenian version Serbian version Swedish version Tagalog version Ukrainian version Vietnamese version Chinese version Turkish version
EDAboard.com map