EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

ISERDES2 divide factor

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - FPGA - ISERDES2 divide factor

jonpry
Guest

Wed May 30, 2012 10:50 pm   



Hi all,

I have a Spartan-6 LX45 board with a whole bunch of lvds going in
and out at a rate of 780mbps. After running out of pins I was forced
to put two lvds receiving pairs into a different bank from the rest of
the bus. To make matters worse this bank has an active MCB. All of
the tx/rx lvds is synchronous with a clock I have inside the fpga so
both transmit and receive are handled through the BUFPLL method
suggested in XAPP1064. Receive channels are using the differential
phase detector mode of IDELAY2 and ISERDES2.

The bank with the MCB presents a unique challenge because the MCB
makes use of both BUFPLL resources available along that edge of the
device. On the bright side I am able to run the memory interface at
the same 780mbps potentially allowing me to use the same BUFPLL
technique used on other edges of the device. The problem is that the
MCB requires the BUFPLL to be run with DIVIDE=2 essentially causing
the fabric side of the ISERDES2 to run at 390mhz!

In the XAPP1064 source code I found the following note relating to
the instantiation of ISERDES2:

DATA_WIDTH => 6, -- SERDES word width. This should match the
setting is BUFPLL

I wonder what exactly "should" means. Say that I have BUFPLL with
divide=2 and ISERDES with width=6. What is really going to happen?
Looking at figure 3-1 on page 80 of UG381. It looks to me as though it
would work fine. A bitslip machine would be able to line of which of
the 3 strobes was actually the correct one.


Guest

Thu Jun 28, 2012 11:47 pm   



For posterity.

This actually does work in hardware. Although I had to implement my own bitslip in addition to the builtin one. I suspect it suffers from the same problem as all Xapp1064 receivers. Ie data corruption if the IDELAY phase shift crosses from -180deg to +180deg but that is a whole different animal.


Guest

Wed Jan 04, 2017 10:06 pm   



Le mercredi 30 mai 2012 16:50:12 UTC-4, jonpry a écrit :
Quote:
Hi all,

I have a Spartan-6 LX45 board with a whole bunch of lvds going in
and out at a rate of 780mbps. After running out of pins I was forced
to put two lvds receiving pairs into a different bank from the rest of
the bus. To make matters worse this bank has an active MCB. All of
the tx/rx lvds is synchronous with a clock I have inside the fpga so
both transmit and receive are handled through the BUFPLL method
suggested in XAPP1064. Receive channels are using the differential
phase detector mode of IDELAY2 and ISERDES2.

The bank with the MCB presents a unique challenge because the MCB
makes use of both BUFPLL resources available along that edge of the
device. On the bright side I am able to run the memory interface at
the same 780mbps potentially allowing me to use the same BUFPLL
technique used on other edges of the device. The problem is that the
MCB requires the BUFPLL to be run with DIVIDE=2 essentially causing
the fabric side of the ISERDES2 to run at 390mhz!

In the XAPP1064 source code I found the following note relating to
the instantiation of ISERDES2:

DATA_WIDTH => 6, -- SERDES word width. This should match the
setting is BUFPLL

I wonder what exactly "should" means. Say that I have BUFPLL with
divide=2 and ISERDES with width=6. What is really going to happen?
Looking at figure 3-1 on page 80 of UG381. It looks to me as though it
would work fine. A bitslip machine would be able to line of which of
the 3 strobes was actually the correct one.



Guest

Wed Jan 04, 2017 10:08 pm   



Le mercredi 30 mai 2012 16:50:12 UTC-4, jonpry a écrit :
Quote:
Hi all,

I have a Spartan-6 LX45 board with a whole bunch of lvds going in
and out at a rate of 780mbps. After running out of pins I was forced
to put two lvds receiving pairs into a different bank from the rest of
the bus. To make matters worse this bank has an active MCB. All of
the tx/rx lvds is synchronous with a clock I have inside the fpga so
both transmit and receive are handled through the BUFPLL method
suggested in XAPP1064. Receive channels are using the differential
phase detector mode of IDELAY2 and ISERDES2.

The bank with the MCB presents a unique challenge because the MCB
makes use of both BUFPLL resources available along that edge of the
device. On the bright side I am able to run the memory interface at
the same 780mbps potentially allowing me to use the same BUFPLL
technique used on other edges of the device. The problem is that the
MCB requires the BUFPLL to be run with DIVIDE=2 essentially causing
the fabric side of the ISERDES2 to run at 390mhz!

In the XAPP1064 source code I found the following note relating to
the instantiation of ISERDES2:

DATA_WIDTH => 6, -- SERDES word width. This should match the
setting is BUFPLL

I wonder what exactly "should" means. Say that I have BUFPLL with
divide=2 and ISERDES with width=6. What is really going to happen?
Looking at figure 3-1 on page 80 of UG381. It looks to me as though it
would work fine. A bitslip machine would be able to line of which of
the 3 strobes was actually the correct one.


elektroda.net NewsGroups Forum Index - FPGA - ISERDES2 divide factor

Ask a question - edaboard.com

Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
RTV map EDAboard.com map News map EDAboard.eu map EDAboard.de map EDAboard.co.uk map