Fri Oct 12, 2018 4:45 pm
I have codes wanting to have output as a Verilog code, Is there any tool which can do it?
Sat Oct 13, 2018 8:45 am
What do you mean? System Verilog is completely based on Verilog + extra. What kind of output do you need? There won’t be a tool such as that. (Not a perfect example but would be like having a tool to turn C++ into C.)