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Is there a verilog syntax beginning with '$'?

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elektroda.net NewsGroups Forum Index - Verilog Language - Is there a verilog syntax beginning with '$'?

Robert Willy
Guest

Sat Sep 29, 2018 9:45 pm   



Hi, everyone:
Verilog is not my daily design tool, but it is required a general familiarity
in a job interview. I once noticed a verilog syntax beginning with '$'. I had
found online forum discussing about it, but I can't remember the detail syntax
now.

Could you verilog expert tell me such a usage ('$____')?


Thanks,

Robert Willy
Guest

Sat Sep 29, 2018 10:45 pm   



On Saturday, September 29, 2018 at 3:34:31 PM UTC-5, Robert Willy wrote:
Quote:
Hi, everyone:
Verilog is not my daily design tool, but it is required a general familiarity
in a job interview. I once noticed a verilog syntax beginning with '$'. I had
found online forum discussing about it, but I can't remember the detail syntax
now.

Could you verilog expert tell me such a usage ('$____')?


Thanks,


Surely, it is not about $display, $write etc. It is a not usual usage, but I
want to know it now.

Robert Willy
Guest

Sun Sep 30, 2018 4:45 am   



On Saturday, September 29, 2018 at 3:34:31 PM UTC-5, Robert Willy wrote:
Quote:
Hi, everyone:
Verilog is not my daily design tool, but it is required a general familiarity
in a job interview. I once noticed a verilog syntax beginning with '$'. I had
found online forum discussing about it, but I can't remember the detail syntax
now.

Could you verilog expert tell me such a usage ('$____')?


Thanks,


I got it. It is $signed. Thanks.

elektroda.net NewsGroups Forum Index - Verilog Language - Is there a verilog syntax beginning with '$'?

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