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is it a library problem for synopsys and mentor?

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Tracy
Guest

Tue Feb 17, 2004 4:59 pm   



Dear all,

I'm a newcomer to this group, and I'd like to say hello to everybody. :)

I've encountered with a problem during synthesis. I used synopsys
design analyzer to synthesize my RTL design without technology-dependent
mapping. After this, a gate-level design are generated. I found out that
in this design, all the basic gates are replaced with components named
GTECH_XXX, i.e. xor gate -> GTECH_XOR. I tried to use the synopsis vhdl
compiler to compile this gate-level design, everything is OK. But when I
did the same thing with mentor graphics compiler, some warnings occured,
reporting "No default binding components for those cells".

I once checked the directory for synopsys, yes, there is a
subdirectory for "gtech", but I could not find the corresponding
directory or library in Mentor.

My question is: is "Gtech" a standard library? If so, why mentor
cannot identify the basic cells? How to solve thsi library problem if I
want to use synopsis synthesis tool together with mentor graphics dft
tools(because for the dft tools, they can only regard those GTECH_ cells
as black boxes)?

Thanks in advance! :)

Tracy

Metin Yerlikaya
Guest

Tue Feb 17, 2004 11:34 pm   



Hi,
GTECH is something like generic tech. So its not really a library, its
something intermediate. Any GTECH component can be synthesized in many different
ways into real gatelevel( based on the library of your vendor ).
I think no other tool except Synopsys synthesis tools can deal with
GTECH.

Metin



Tracy <zhoujn_at_ra.informatik.uni-stuttgart.de> wrote in message news:<c0tdpn$3gi$1_at_inf2.informatik.uni-stuttgart.de>...
Quote:
Dear all,

I'm a newcomer to this group, and I'd like to say hello to everybody. :)

I've encountered with a problem during synthesis. I used synopsys
design analyzer to synthesize my RTL design without technology-dependent
mapping. After this, a gate-level design are generated. I found out that
in this design, all the basic gates are replaced with components named
GTECH_XXX, i.e. xor gate -> GTECH_XOR. I tried to use the synopsis vhdl
compiler to compile this gate-level design, everything is OK. But when I
did the same thing with mentor graphics compiler, some warnings occured,
reporting "No default binding components for those cells".

I once checked the directory for synopsys, yes, there is a
subdirectory for "gtech", but I could not find the corresponding
directory or library in Mentor.

My question is: is "Gtech" a standard library? If so, why mentor
cannot identify the basic cells? How to solve thsi library problem if I
want to use synopsis synthesis tool together with mentor graphics dft
tools(because for the dft tools, they can only regard those GTECH_ cells
as black boxes)?

Thanks in advance! :)

Tracy


Amit Gupta
Guest

Thu Feb 19, 2004 5:44 pm   



Hi,

You can try this... Write a simple technology-map file which contains
only AND/OR/NOT/BUF primitive and compile through dc-compiler with your
own library file as the target technology. I would assume that the
synthesized netlist would be a valid read-all verilog netlist.

Cheers,
-Amit
Metin Yerlikaya wrote:
Quote:
Hi,
GTECH is something like generic tech. So its not really a library, its
something intermediate. Any GTECH component can be synthesized in many different
ways into real gatelevel( based on the library of your vendor ).
I think no other tool except Synopsys synthesis tools can deal with
GTECH.

Metin



Tracy <zhoujn_at_ra.informatik.uni-stuttgart.de> wrote in message news:<c0tdpn$3gi$1_at_inf2.informatik.uni-stuttgart.de>...

Dear all,

I'm a newcomer to this group, and I'd like to say hello to everybody. :)

I've encountered with a problem during synthesis. I used synopsys
design analyzer to synthesize my RTL design without technology-dependent
mapping. After this, a gate-level design are generated. I found out that
in this design, all the basic gates are replaced with components named
GTECH_XXX, i.e. xor gate -> GTECH_XOR. I tried to use the synopsis vhdl
compiler to compile this gate-level design, everything is OK. But when I
did the same thing with mentor graphics compiler, some warnings occured,
reporting "No default binding components for those cells".

I once checked the directory for synopsys, yes, there is a
subdirectory for "gtech", but I could not find the corresponding
directory or library in Mentor.

My question is: is "Gtech" a standard library? If so, why mentor
cannot identify the basic cells? How to solve thsi library problem if I
want to use synopsis synthesis tool together with mentor graphics dft
tools(because for the dft tools, they can only regard those GTECH_ cells
as black boxes)?

Thanks in advance! :)

Tracy


Tracy
Guest

Fri Feb 20, 2004 11:39 am   



Hi,

Thanks a lot for your reply! Smile
Currently I synthesized my design using MTC45000 as the target
library. And in order to let the Mentor Graphics DFT tools work with the
synthesized design, I made some modification to the ATPG libray(
adk.aptg, I guess maybe this libray is the one for ASIC Design Kit
provided by Mentor Graphics) by manually adding some specifications of
the basic cells which appear in the synthesized design but not in the
ATPG library. It seems to work if I can correctly figure out the
functionality/structure for the basic cells in the schematic after
synthesis. But the problem occurs when some of the leaf cells in the
schematic are just represented as blocks with inputs and outputs. Such
translation is no longer feasible. Sad
I just wonder whether there is the corresponding atpg library for
MTC45000? And where can I get it?
Have a nice weekend!
regards,

Amit Gupta wrote:
Quote:
Hi,

You can try this... Write a simple technology-map file which contains
only AND/OR/NOT/BUF primitive and compile through dc-compiler with your
own library file as the target technology. I would assume that the
synthesized netlist would be a valid read-all verilog netlist.

Cheers,
-Amit
Metin Yerlikaya wrote:

Hi, GTECH is something like generic tech. So its not really a library,
its something intermediate. Any GTECH component can be synthesized in
many different
ways into real gatelevel( based on the library of your vendor ).
I think no other tool except Synopsys synthesis tools can deal with
GTECH.

Metin



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