chetan
Guest
Thu Sep 08, 2011 12:46 pm
IN what kind of situation we will use IODELAY element in both clock
path and data path.
In this situation will both have variable delay type or may bot be the
case.
do any one can tell me some real time situation where we will use this
Gabor
Guest
Thu Sep 08, 2011 2:36 pm
chetan wrote:
Quote:
IN what kind of situation we will use IODELAY element in both clock
path and data path.
In this situation will both have variable delay type or may bot be the
case.
do any one can tell me some real time situation where we will use this
I'm not sure that this is really a Verilog issue, perhaps comp.arch.fpga
or the Xilinx forums would be a better venue.
Most Xilinx parts have the ability to either use or bypass the variable
delay element. If your clock and data are fairly closely aligned, but
not close enough for the application, then adding the IODELAY to one
but not the other (e.g. clock but not data) might result in too
coarse an adjustment that cannot make the alignment correct even with
zero specified for the variable delay. In that case you could add
the delay element to all signals and only vary the clock while keeping
the data delay fixed at "zero."
-- Gabor
