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Jim Thompson
Guest

Thu Jan 12, 2017 8:30 am   



On Wed, 11 Jan 2017 19:52:44 -0500, Phil Hobbs
<pcdhSpamMeSenseless_at_electrooptical.net> wrote:

Quote:
On 01/11/2017 03:45 PM, Jim Thompson wrote:
On Wed, 11 Jan 2017 15:33:44 -0500, Phil Hobbs
pcdhSpamMeSenseless_at_electrooptical.net> wrote:

On 01/11/2017 02:31 PM, Jim Thompson wrote:
On Tue, 10 Jan 2017 11:56:47 -0500, Phil Hobbs
pcdhSpamMeSenseless_at_electrooptical.net> wrote:

On 01/10/2017 11:49 AM, bitrex wrote:
Saw this interesting circuit while trolling around on patent sites
looking for inspiration:

https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US20090243720.pdf


It looks like the negative capacitance is proportional to the
transconductance of "Qn2", i.e. proportional to the bias currents. In
the patent they seem to be using it to null the gate/source capacitance
on the MOSFET output stage of power amps.

Is anyone aware of any similar topologies for grounded negative
capacitances? I've seen some other topologies using a couple transistors
but they all seemed to require transformers on the input port.

It might be useful to have a circuit like that where the negative
capacitance was proportional to a control voltage.


I'm surprised that you could patent that in 2009.

The usual negative capacitor is a noninverting amp with a gain slightly
larger than unity, and a cap connected from output to + input.

They're very rarely useful, because any phase lag gives the input a
negative conductance as well as susceptance, so unless the amp is way
faster than what you're connecting it to, it'll oscillate before the
total capacitance goes away.

(I did use one last year, but that's almost a first.)

Cheers

Phil Hobbs

Digging thru my past designs I find a capacitance multiplier based on
the AD835... good upwards of 250MHz.

I haven't tried, but I'd guess that one could twist it around to be a
negative capacitance... though I'd expect oscillation Wink

...Jim Thompson


Sure, my negative capacitor was based on an ADA4817 (1.4 GHz). That
gave me enough space to roll off the gain before the phase shift got too
ugly.

Cheers

Phil Hobbs

That'll cover the audio range >:-}

...Jim Thompson

Well, sometimes a bigger hammer is better. ;)

Cheers

Phil Hobbs


Yep Wink

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Phil Hobbs
Guest

Thu Jan 12, 2017 8:30 am   



On 01/11/2017 09:07 PM, Jim Thompson wrote:
Quote:
On Wed, 11 Jan 2017 19:55:45 -0500, Phil Hobbs
pcdhSpamMeSenseless_at_electrooptical.net> wrote:

On 01/11/2017 06:33 PM, bitrex wrote:
On 01/10/2017 03:11 PM, Phil Hobbs wrote:
On 01/10/2017 02:09 PM, John Larkin wrote:
On Tue, 10 Jan 2017 11:49:01 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

Saw this interesting circuit while trolling around on patent sites
looking for inspiration:

https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US20090243720.pdf


It looks like the negative capacitance is proportional to the
transconductance of "Qn2", i.e. proportional to the bias currents. In
the patent they seem to be using it to null the gate/source capacitance
on the MOSFET output stage of power amps.

Is anyone aware of any similar topologies for grounded negative
capacitances? I've seen some other topologies using a couple
transistors
but they all seemed to require transformers on the input port.

It might be useful to have a circuit like that where the negative
capacitance was proportional to a control voltage.

That is pretty cool, a potential replacement for a varicap. Varicaps
can be a real pain.

Reactance modulators have been around for a long time. They're
generally crap because the amplifier is too slow and noisy to do a good
job at it.

If you replace the output transistor with a diff pair, you could make a
negative-capacitance varactor, which would be neat, I agree. You could
even make its bias stable by running the diff pair as an exponentiator,
so that the extra DC gets dumped to ground but the rest of the circuit
sees a constant value.

Cheers

Phil Hobbs


Some issues I have with the circuit analysis given by the patent (and JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs

What is troubling... it's essentially a capacitively-coupled Schmitt.

...Jim Thompson


Well, it'll go nuts if the source impedance isn't within the design
range, for sure.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

Jim Thompson
Guest

Thu Jan 12, 2017 8:30 am   



On Wed, 11 Jan 2017 19:55:45 -0500, Phil Hobbs
<pcdhSpamMeSenseless_at_electrooptical.net> wrote:

Quote:
On 01/11/2017 06:33 PM, bitrex wrote:
On 01/10/2017 03:11 PM, Phil Hobbs wrote:
On 01/10/2017 02:09 PM, John Larkin wrote:
On Tue, 10 Jan 2017 11:49:01 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

Saw this interesting circuit while trolling around on patent sites
looking for inspiration:

https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US20090243720.pdf


It looks like the negative capacitance is proportional to the
transconductance of "Qn2", i.e. proportional to the bias currents. In
the patent they seem to be using it to null the gate/source capacitance
on the MOSFET output stage of power amps.

Is anyone aware of any similar topologies for grounded negative
capacitances? I've seen some other topologies using a couple
transistors
but they all seemed to require transformers on the input port.

It might be useful to have a circuit like that where the negative
capacitance was proportional to a control voltage.

That is pretty cool, a potential replacement for a varicap. Varicaps
can be a real pain.

Reactance modulators have been around for a long time. They're
generally crap because the amplifier is too slow and noisy to do a good
job at it.

If you replace the output transistor with a diff pair, you could make a
negative-capacitance varactor, which would be neat, I agree. You could
even make its bias stable by running the diff pair as an exponentiator,
so that the extra DC gets dumped to ground but the rest of the circuit
sees a constant value.

Cheers

Phil Hobbs


Some issues I have with the circuit analysis given by the patent (and JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


What is troubling... it's essentially a capacitively-coupled Schmitt.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |


Guest

Thu Jan 12, 2017 5:03 pm   



Quote:
The niggle I have is that since there is no DC path from the left
transistor to the current source on the right,


That's the whole point of the circuit. Just assume perfect current sources and transistors with alpha=1.

Quote:
it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources


Of course it will--but you'll wind up with 1Gohm to -1MV or something like that.

Cheers

Phil Hobbs

bitrex
Guest

Thu Jan 12, 2017 9:44 pm   



On 01/11/2017 07:55 PM, Phil Hobbs wrote:
Quote:
On 01/11/2017 06:33 PM, bitrex wrote:
On 01/10/2017 03:11 PM, Phil Hobbs wrote:
On 01/10/2017 02:09 PM, John Larkin wrote:
On Tue, 10 Jan 2017 11:49:01 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

Saw this interesting circuit while trolling around on patent sites
looking for inspiration:

https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US20090243720.pdf



It looks like the negative capacitance is proportional to the
transconductance of "Qn2", i.e. proportional to the bias currents. In
the patent they seem to be using it to null the gate/source
capacitance
on the MOSFET output stage of power amps.

Is anyone aware of any similar topologies for grounded negative
capacitances? I've seen some other topologies using a couple
transistors
but they all seemed to require transformers on the input port.

It might be useful to have a circuit like that where the negative
capacitance was proportional to a control voltage.

That is pretty cool, a potential replacement for a varicap. Varicaps
can be a real pain.

Reactance modulators have been around for a long time. They're
generally crap because the amplifier is too slow and noisy to do a good
job at it.

If you replace the output transistor with a diff pair, you could make a
negative-capacitance varactor, which would be neat, I agree. You could
even make its bias stable by running the diff pair as an exponentiator,
so that the extra DC gets dumped to ground but the rest of the circuit
sees a constant value.

Cheers

Phil Hobbs


Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense. If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.

It looks to me like it can't be nothin'; it can't be infinite, can't be
zero, it has to be something. If the magnitude of the admittance has to
be something, then I don't see the mathematical justification for
treating it as if it's nothing in the small-signal analysis.

Jim Thompson
Guest

Thu Jan 12, 2017 10:05 pm   



On Thu, 12 Jan 2017 09:44:07 -0500, bitrex
<bitrex_at_de.lete.earthlink.net> wrote:

Quote:
On 01/11/2017 07:55 PM, Phil Hobbs wrote:
On 01/11/2017 06:33 PM, bitrex wrote:


[snip]

Quote:

Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense.


Nonsense. Show us how you analyzed it.

Quote:
If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.


Bypassing the resistor makes it NOT-LIKE a current source.

Quote:

It looks to me like it can't be nothin'; it can't be infinite,


Bull-crap! My analysis assumed infinite.

Quote:
can't be
zero, it has to be something. If the magnitude of the admittance has to
be something, then I don't see the mathematical justification for
treating it as if it's nothing in the small-signal analysis.


I was fortunate enough to have Harry B. Lee for circuit analysis
because I was in the Honors EE program. Thus I didn't have to endure
the Guillemin nonsense... so I'm quite comfortable doing nodal and
loop analyses.

I suggest you study up Wink

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |


Guest

Thu Jan 12, 2017 10:45 pm   



Quote:
though many
(like the Mellin transform) don't have much application to engineering.


Mellin transforms are dead useful in the design of scanning systems (e.g. computing the linespread function from the pointspread) and in deriving asymptotic series. There's a really great Dover book on asymptotic methods that goes into all sorts of interesting detail on that. (It's at the lab, and I'm back in bed, so I don't have the exact details.) :(

Cheers

Phil Hobbs

bitrex
Guest

Thu Jan 12, 2017 11:11 pm   



On 01/12/2017 10:05 AM, Jim Thompson wrote:
Quote:
On Thu, 12 Jan 2017 09:44:07 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/11/2017 07:55 PM, Phil Hobbs wrote:
On 01/11/2017 06:33 PM, bitrex wrote:

[snip]


Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense.

Nonsense. Show us how you analyzed it.

If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.

Bypassing the resistor makes it NOT-LIKE a current source.


It looks to me like it can't be nothin'; it can't be infinite,

Bull-crap! My analysis assumed infinite.


You assumed the admittance of the right current source was infinite,
i.e. a dead short? Well...

It looked to me like the analysis was along the lines of the loop
analysis for a diff-pair with a current source in the tail. With a
DC-coupled diff-pair drawing say 2mA and a common mode signal, both
inputs go up, and the current source draws 2mA. In differential mode one
transistor decreases conductance to 1.9mA, the other increases to 2.1mA,
and the current source draws...2mA. Its conductance never changes.

If the source's conductance never changes with signal, then from a small
signal AC analysis perspective it's fine to treat it as if it has an
infinite real impedance (zero admittance.) It's just a DC source.

My point of contention is that it looks like in this circuit the
conductance of the right current source must vary with signal. If it
does that, then the magnitude of its admittance must be finite, in which
case it can't have a infinite (real) impedance.

Quote:
I was fortunate enough to have Harry B. Lee for circuit analysis
because I was in the Honors EE program. Thus I didn't have to endure
the Guillemin nonsense... so I'm quite comfortable doing nodal and
loop analyses.

I suggest you study up Wink

...Jim Thompson


Who's Guillemin, this guy?

http://math.mit.edu/directory/profile.php?pid=87

Jim Thompson
Guest

Thu Jan 12, 2017 11:15 pm   



"NegativeCapacitor.pdf" on the S.E.D/Schematics Page of my
website has been updated to include simulations showing the regions of
instability.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Jim Thompson
Guest

Thu Jan 12, 2017 11:21 pm   



On Thu, 12 Jan 2017 11:11:09 -0500, bitrex
<bitrex_at_de.lete.earthlink.net> wrote:

Quote:
On 01/12/2017 10:05 AM, Jim Thompson wrote:
On Thu, 12 Jan 2017 09:44:07 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/11/2017 07:55 PM, Phil Hobbs wrote:
On 01/11/2017 06:33 PM, bitrex wrote:

[snip]


Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense.

Nonsense. Show us how you analyzed it.

If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.

Bypassing the resistor makes it NOT-LIKE a current source.


It looks to me like it can't be nothin'; it can't be infinite,

Bull-crap! My analysis assumed infinite.

You assumed the admittance of the right current source was infinite,
i.e. a dead short? Well...


Infinite IMPEDANCE

Quote:

It looked to me like the analysis was along the lines of the loop
analysis for a diff-pair with a current source in the tail. With a
DC-coupled diff-pair drawing say 2mA and a common mode signal, both
inputs go up, and the current source draws 2mA. In differential mode one
transistor decreases conductance to 1.9mA, the other increases to 2.1mA,
and the current source draws...2mA. Its conductance never changes.

If the source's conductance never changes with signal, then from a small
signal AC analysis perspective it's fine to treat it as if it has an
infinite real impedance (zero admittance.) It's just a DC source.

My point of contention is that it looks like in this circuit the
conductance of the right current source must vary with signal. If it
does that, then the magnitude of its admittance must be finite, in which
case it can't have a infinite (real) impedance.


You are hand-waving instead of analyzing. You apparently have no clue
how to do small-signal AC analysis.

I have reposted my NegativeCapacitor.pdf...

"NegativeCapacitor.pdf" on the S.E.D/Schematics Page of my
website has been updated to include simulations showing the regions of
instability.

For amusement I will also do the simulations with ideal devices and
see what results.

Quote:

I was fortunate enough to have Harry B. Lee for circuit analysis
because I was in the Honors EE program. Thus I didn't have to endure
the Guillemin nonsense... so I'm quite comfortable doing nodal and
loop analyses.

I suggest you study up Wink

...Jim Thompson


Who's Guillemin, this guy?

http://math.mit.edu/directory/profile.php?pid=87


Nope... ERNST Guillemin.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

bitrex
Guest

Thu Jan 12, 2017 11:37 pm   



On 01/12/2017 11:21 AM, Jim Thompson wrote:
Quote:
On Thu, 12 Jan 2017 11:11:09 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/12/2017 10:05 AM, Jim Thompson wrote:
On Thu, 12 Jan 2017 09:44:07 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/11/2017 07:55 PM, Phil Hobbs wrote:
On 01/11/2017 06:33 PM, bitrex wrote:

[snip]


Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense.

Nonsense. Show us how you analyzed it.

If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.

Bypassing the resistor makes it NOT-LIKE a current source.


It looks to me like it can't be nothin'; it can't be infinite,

Bull-crap! My analysis assumed infinite.

You assumed the admittance of the right current source was infinite,
i.e. a dead short? Well...

Infinite IMPEDANCE


It looked to me like the analysis was along the lines of the loop
analysis for a diff-pair with a current source in the tail. With a
DC-coupled diff-pair drawing say 2mA and a common mode signal, both
inputs go up, and the current source draws 2mA. In differential mode one
transistor decreases conductance to 1.9mA, the other increases to 2.1mA,
and the current source draws...2mA. Its conductance never changes.

If the source's conductance never changes with signal, then from a small
signal AC analysis perspective it's fine to treat it as if it has an
infinite real impedance (zero admittance.) It's just a DC source.

My point of contention is that it looks like in this circuit the
conductance of the right current source must vary with signal. If it
does that, then the magnitude of its admittance must be finite, in which
case it can't have a infinite (real) impedance.

You are hand-waving instead of analyzing. You apparently have no clue
how to do small-signal AC analysis.


Small-signal AC analysis is based on a set of assumptions, and my point
is that I'm not sure that considering the rightmost current source to
have infinite real impedance for AC is a valid assumption. I'm willing
to concede that I'm wrong, but I'd like to know why.

Quote:
"NegativeCapacitor.pdf" on the S.E.D/Schematics Page of my
website has been updated to include simulations showing the regions of
instability.

For amusement I will also do the simulations with ideal devices and
see what results.


Much appreciated.

Jim Thompson
Guest

Thu Jan 12, 2017 11:55 pm   



"NegativeCapacitor.pdf" on the S.E.D/Schematics Page of my
website has been further updated to include simulations using ideal
active devices.

With RIN = 0, you can obtain a perfectly ideal negative capacitor.

Ideal devices can be closely approximated on an integrated circuit,
thus explaining why the patent has been revived.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Jim Thompson
Guest

Thu Jan 12, 2017 11:59 pm   



On Thu, 12 Jan 2017 11:37:02 -0500, bitrex
<bitrex_at_de.lete.earthlink.net> wrote:

Quote:
On 01/12/2017 11:21 AM, Jim Thompson wrote:
On Thu, 12 Jan 2017 11:11:09 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/12/2017 10:05 AM, Jim Thompson wrote:
On Thu, 12 Jan 2017 09:44:07 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/11/2017 07:55 PM, Phil Hobbs wrote:
On 01/11/2017 06:33 PM, bitrex wrote:

[snip]


Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense.

Nonsense. Show us how you analyzed it.

If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.

Bypassing the resistor makes it NOT-LIKE a current source.


It looks to me like it can't be nothin'; it can't be infinite,

Bull-crap! My analysis assumed infinite.

You assumed the admittance of the right current source was infinite,
i.e. a dead short? Well...

Infinite IMPEDANCE


It looked to me like the analysis was along the lines of the loop
analysis for a diff-pair with a current source in the tail. With a
DC-coupled diff-pair drawing say 2mA and a common mode signal, both
inputs go up, and the current source draws 2mA. In differential mode one
transistor decreases conductance to 1.9mA, the other increases to 2.1mA,
and the current source draws...2mA. Its conductance never changes.

If the source's conductance never changes with signal, then from a small
signal AC analysis perspective it's fine to treat it as if it has an
infinite real impedance (zero admittance.) It's just a DC source.

My point of contention is that it looks like in this circuit the
conductance of the right current source must vary with signal. If it
does that, then the magnitude of its admittance must be finite, in which
case it can't have a infinite (real) impedance.

You are hand-waving instead of analyzing. You apparently have no clue
how to do small-signal AC analysis.

Small-signal AC analysis is based on a set of assumptions, and my point
is that I'm not sure that considering the rightmost current source to
have infinite real impedance for AC is a valid assumption. I'm willing
to concede that I'm wrong, but I'd like to know why.


It'll appear in parallel with re2 in a small-signal analysis. If it's
large compared to re2 it's effect will be negligible.

Quote:

"NegativeCapacitor.pdf" on the S.E.D/Schematics Page of my
website has been updated to include simulations showing the regions of
instability.

For amusement I will also do the simulations with ideal devices and
see what results.

Much appreciated.


Done. See..

Message-ID: <k1df7cpnfgvc83icjnve25du3r1ga1t434_at_4ax.com>

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

bitrex
Guest

Fri Jan 13, 2017 12:09 am   



On 01/12/2017 11:59 AM, Jim Thompson wrote:
Quote:
On Thu, 12 Jan 2017 11:37:02 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/12/2017 11:21 AM, Jim Thompson wrote:
On Thu, 12 Jan 2017 11:11:09 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/12/2017 10:05 AM, Jim Thompson wrote:
On Thu, 12 Jan 2017 09:44:07 -0500, bitrex
bitrex_at_de.lete.earthlink.net> wrote:

On 01/11/2017 07:55 PM, Phil Hobbs wrote:
On 01/11/2017 06:33 PM, bitrex wrote:

[snip]


Some issues I have with the circuit analysis given by the patent (and
JT):

First thing is that it's not unstable for all component values; if
they're appropriately selected it "does what it says on the tin."

Second issue I'll get to by a bit of rhetoric: the circuit in the
diagram is composed entirely of ideal components with no negative
reactances anywhere that I can see. So, where is the "magic" happening
that makes the impedance looking into the input port negative? Yeah it
has positive feedback but positive feedback doesn't make magic.

It's pretty simple. When the input goes up, the follower dumps current
into the emitter of the output transistor, which _subtracts_ current
from the collector circuit. This works because both transistors have
current-source biasing.

Cheers

Phil Hobbs


The niggle I have is that since there is no DC path from the left
transistor to the current source on the right, it looks to me like the
magnitude of the admittance (conductance + susceptance) of the current
source on the right must have some constant, finite, non-zero value.

The circuit just won't work if you try to replace both current sources
with "large-value resistor" approximations to current sources. Not even
in a small signal analysis sense.

Nonsense. Show us how you analyzed it.

If you replace the one on the left
with a large-value resistor and the one on the right with a resistor
bypassed by an appropriately-sized capacitor, however, it seems to work
material equivalently from the perspective of the input port.

Bypassing the resistor makes it NOT-LIKE a current source.


It looks to me like it can't be nothin'; it can't be infinite,

Bull-crap! My analysis assumed infinite.

You assumed the admittance of the right current source was infinite,
i.e. a dead short? Well...

Infinite IMPEDANCE


It looked to me like the analysis was along the lines of the loop
analysis for a diff-pair with a current source in the tail. With a
DC-coupled diff-pair drawing say 2mA and a common mode signal, both
inputs go up, and the current source draws 2mA. In differential mode one
transistor decreases conductance to 1.9mA, the other increases to 2.1mA,
and the current source draws...2mA. Its conductance never changes.

If the source's conductance never changes with signal, then from a small
signal AC analysis perspective it's fine to treat it as if it has an
infinite real impedance (zero admittance.) It's just a DC source.

My point of contention is that it looks like in this circuit the
conductance of the right current source must vary with signal. If it
does that, then the magnitude of its admittance must be finite, in which
case it can't have a infinite (real) impedance.

You are hand-waving instead of analyzing. You apparently have no clue
how to do small-signal AC analysis.

Small-signal AC analysis is based on a set of assumptions, and my point
is that I'm not sure that considering the rightmost current source to
have infinite real impedance for AC is a valid assumption. I'm willing
to concede that I'm wrong, but I'd like to know why.

It'll appear in parallel with re2 in a small-signal analysis. If it's
large compared to re2 it's effect will be negligible.


I did do an analysis without making the assumption that the AC impedance
of the right current source is infinite, and yes it does appear that in
the limiting case it reduces to the equation given in the patent. A
legible version will have to wait until I pick up more graph paper...Wink

Jim Thompson
Guest

Fri Jan 13, 2017 12:27 am   



On Thu, 12 Jan 2017 12:09:28 -0500, bitrex
<bitrex_at_de.lete.earthlink.net> wrote:

>On 01/12/2017 11:59 AM, Jim Thompson wrote:

[snip]

Quote:

It'll appear in parallel with re2 in a small-signal analysis. If it's
large compared to re2 it's effect will be negligible.

I did do an analysis without making the assumption that the AC impedance
of the right current source is infinite, and yes it does appear that in
the limiting case it reduces to the equation given in the patent. A
legible version will have to wait until I pick up more graph paper...Wink


Those skilled in the art will recognize the equations (in the patent)
just above and just below [0028], match my derivation, if you make the
identity substitution jw==s (I was taught Heaviside notation at about
age 20 Wink

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

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