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Insert transient voltage on internal signal of a module - Ve

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Raphael Viera
Guest

Tue Oct 22, 2019 8:45 pm   



I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can insert transient voltages (like glitches) at the inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue?

Example: glitch in a clock signal (https://stackoverflow.com/questions/2251465/producing-a-clock-glitch-in-a-verilog-design)

always begin: inject_clk_glitch
#1 force clk = 1;
#1 force clk = 0;
#1 release clk;
end

HT-Lab
Guest

Fri Oct 25, 2019 10:45 am   



On 22/10/2019 20:40, Raphael Viera wrote:
Quote:


I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can insert transient voltages (like glitches) at the inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue?

Example: glitch in a clock signal (https://stackoverflow.com/questions/2251465/producing-a-clock-glitch-in-a-verilog-design)

always begin: inject_clk_glitch
#1 force clk = 1;
#1 force clk = 0;
#1 release clk;
end


If you have access to Modelsim/Questa/Riviera have a look a look at
signalspy which is more capable than Verilog/VHDL's force language
construct. You could also look at the Tcl force command which has
similar capabilities.

Both should be able to force a signal/logic/etc in your netlist.

Good luck,

Hans
www.ht-lab.com

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