Joseph
Guest
Wed Apr 13, 2011 9:00 am
Hi all,
I am synthesizing a well known add-shift multiplication routine. I have the Multiplier register Q ,an addition register A and a Carry register C (the carry of the adder) which are concatenated together to give the multiplication results. For the shifting part I am writing the following code:
Q <= A(0) & Q(3 downto 1);
A <= C & A(3 downto 1);
That should perform a right shift in both A and Q. This is being done in a clocked process so registers are being created (that is working). When synthesizing using Xilinx and simulating using ISIM the right shift is being performed but the LSB of Q never has the correct value.
Am I coding it incorrectly in Xilinx?
Regards,
Joseph
Thomas Stanka
Guest
Wed Apr 13, 2011 2:28 pm
On 13 Apr., 09:00, Joseph <joz...@gmail.com> wrote:
Quote:
Q <= A(0) & Q(3 downto 1);
A <= C & A(3 downto 1);
That should perform a right shift in both A and Q. This is being done in a clocked process so registers are being created (that is working). When synthesizing using Xilinx and simulating using ISIM the right shift is being performed but the LSB of Q never has the correct value.
This code snipplet has to less information. Actually there are plenty
of reasons why a vhdl code simulates different than the synthesis
result of this code. Without further information it is not predictabel
which reason is your problem.
You can not "code it incorrect in Xilinx". But you can easily write
vhdl code which has "misleading" simulation result compared to the
netlist you get after synthesis independend of the used tools.
bye Thomas
Andy
Guest
Wed Apr 13, 2011 4:42 pm
Not enough info. Are the other bits getting "correct" values? How can
you tell that Q(0) is not getting the "correct" value? (What is the
correct value?)
Andy
