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include file problem in verilog plz sort it out ............

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elektroda.net NewsGroups Forum Index - Verilog Language - include file problem in verilog plz sort it out ............

m2star
Guest

Wed Mar 02, 2011 8:30 am   



hi all please check
"module mian(a,b,c);
//parameter A_width=4;
//parameter D_width=8;
`include "C:\Documents and Settings\abc\Desktop\prectice
\info.h"
input [A_width-1:0]a;
input [D_width-1:0]b;
output [D_width-1:0]c;
assign c[D_width-1:0]=b[D_width-1:0];
endmodule"
and info file is like
info.h
"parameter D_width=8;
parameter A_width=4;"
info file is located at mentioned path but I found this error always
** Error: C:/Documents and Settings/abc/Desktop/prectice/main.v(4):
Cannot open `include file "C:Documents and SettingsMOHSIN
GHAFFARDesktopprecticeinfo.h"
im using modelsim 5.7f SE
please reply sooon.................................

gabor
Guest

Wed Mar 02, 2011 6:26 pm   



On Wednesday, March 2, 2011 1:30:24 AM UTC-5, m2star wrote:
Quote:
hi all please check
"module mian(a,b,c);
//parameter A_width=4;
//parameter D_width=8;
`include "C:\Documents and Settings\abc\Desktop\prectice
\info.h"
input [A_width-1:0]a;
input [D_width-1:0]b;
output [D_width-1:0]c;
assign c[D_width-1:0]=b[D_width-1:0];
endmodule"
and info file is like
info.h
"parameter D_width=8;
parameter A_width=4;"
info file is located at mentioned path but I found this error always
** Error: C:/Documents and Settings/abc/Desktop/prectice/main.v(4):
Cannot open `include file "C:Documents and SettingsMOHSIN
GHAFFARDesktopprecticeinfo.h"
im using modelsim 5.7f SE
please reply sooon.................................

You need to use normal slashes in your path, not backslashes
as these are interpreted as escape characters. So change:

`include "C:\Documents and Settings\abc\Desktop\prectice\info.h"

to:

`include "C:/Documents and Settings/abc/Desktop/prectice/info.h"

Also, if you plan to use Xilinx tools with this
project, I would suggest moving your files to a
folder that does not have spaces in the path,
i.e. don't store your projects on the desktop
or in "My Documents." I generally have a main
folder to place projects in directly at the drive
root like:

C:\projects\prectece

-- Gabor

m2star
Guest

Thu Mar 03, 2011 3:15 pm   



On Mar 2, 9:26 pm, gabor <ga...@alacron.com> wrote:
Quote:
On Wednesday, March 2, 2011 1:30:24 AM UTC-5, m2star wrote:
hi all please check
"module mian(a,b,c);
//parameter A_width=4;
//parameter D_width=8;
`include        "C:\Documents and Settings\abc\Desktop\prectice
\info.h"
input   [A_width-1:0]a;
input   [D_width-1:0]b;
output  [D_width-1:0]c;
assign  c[D_width-1:0]=b[D_width-1:0];
endmodule"
and info file is like
info.h
"parameter D_width=8;
parameter A_width=4;"
info file is located at mentioned path but I found this error always
** Error: C:/Documents and Settings/abc/Desktop/prectice/main.v(4):
Cannot open `include file "C:Documents and SettingsMOHSIN
GHAFFARDesktopprecticeinfo.h"
im using modelsim 5.7f SE
please reply sooon.................................

You need to use normal slashes in your path, not backslashes
as these are interpreted as escape characters.  So change:

`include        "C:\Documents and Settings\abc\Desktop\prectice\info.h"

to:

`include        "C:/Documents and Settings/abc/Desktop/prectice/info.h"

Also, if you plan to use Xilinx tools with this
project, I would suggest moving your files to a
folder that does not have spaces in the path,
i.e. don't store your projects on the desktop
or in "My Documents."  I generally have a main
folder to place projects in directly at the drive
root like:

C:\projects\prectece

-- Gabor


i check it out
i found in modelsim both back and forward slash didn't work.........
in modelsim it works only you put you include file in the work
directory and don't specify any path...........
in ISE this methode of back and forward slash both works.............
and Gabor the files i upload is only the test files........
my original files are in their proper location already managed as you
seggest.....
anyway thaks for your help..........................Smile

glen herrmannsfeldt
Guest

Thu Mar 03, 2011 10:35 pm   



m2star <m2star_at_hotmail.com> wrote:

(snip)
Quote:
i found in modelsim both back and forward slash didn't work.........
in modelsim it works only you put you include file in the work
directory and don't specify any path...........
in ISE this methode of back and forward slash both works.............
and Gabor the files i upload is only the test files........
my original files are in their proper location already managed as you

Since at least DOS 3.2, DOS/Windows accepts forward slash in
file open requests. It is only the command line programs that
use forward slash for options, and don't allow them through.

C include files with forward slashes have worked just fine, and C
programmers are used to doing that. If it doesn't work for
modelsim, then it would seem to me that modelsim isn't passing
the name through to the file open call.

-- glen

m2star
Guest

Fri Mar 04, 2011 9:54 am   



On Mar 4, 1:35 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
Quote:
m2star <m2s...@hotmail.com> wrote:

(snip)

i found in modelsim both back and forward slash didn't work.........
in modelsim it works only you put you include file in the work
directory and don't specify any path...........
in ISE this methode of back and forward slash both works.............
and Gabor the files i upload is only the test files........
my original files are in their proper location already managed as you

Since at least DOS 3.2, DOS/Windows accepts forward slash in
file open requests.  It is only the command line programs that
use forward slash for options, and don't allow them through.

C include files with forward slashes have worked just fine, and C
programmers are used to doing that.  If it doesn't work for
modelsim, then it would seem to me that modelsim isn't passing
the name through to the file open call.

-- glen

yeah you are right modelsim read from its work directory
only..............
thanks for your involvement glen............Smile

elektroda.net NewsGroups Forum Index - Verilog Language - include file problem in verilog plz sort it out ............

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