Implementation Issue

Mon Sep 26, 2011 6:10 pm   

Hi Guys,

I'm using the Spartan-3E 1600E Microblaze development kit.
What I'm basically doing is writing to the on board DAC (Linear Tec
LTC2624 Quad DAC), and then reading from the on board ADC (Linear Tec
LTC6912 Dual A/D) whose analog input is connected to the DAC analog output
The data written to the DAC and the data read from the ADC is then mad
available to other modules within my design for analysis/comparison and i
also made available to my LCD driver module so as to display the data o
the LCD.

The problem that I am having is that no data is read back from the ADC (AD
data displayed on LCD is all 0s), however the DAC was successfully written
to (DAC output voltage changed correctly). Now initially I thought I mus
be reading from the ADC incorrectly so I simply brought out debug signals
to a header on the board (J4) so that they could be viewed with a
oscilloscope. The debug signals were connected to the SPI interface signal
TCK, MOSI, MISO, and ADCconv. After bringing out these debug signals, whic
should not effect the design, the design then worked and ADC data was bein
read back correctly.

Now when any combination of the ucf contraints that assign the debu
signals to the header pins are commented out and the design i
re-implemented (not res-synthesised) the design does not work.

Does anyone have any ideas about this? Any help would be greatl
appreciated.

Regards,
James



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Mon Sep 26, 2011 7:20 pm   

In article <_9GdnRsyfMSQXR3TnZ2dnUVZ_rydnZ2d_at_giganews.com>,
James <james.gahan_at_n_o_s_p_a_m.analog.com> wrote:

Timing constraints on the SPI input? Do they exist? Do they pass timing
analysis - for both implementations (with and without the debug connections)?

Depending on how/where you brought out the debug connections, it may
affect timing greatly. If you're not having the tool check the timing,
you're just rolling the dice.

Regards,

Mark

Tue Sep 27, 2011 8:14 am   

Thanks for the help.

As you could probably guess I'm new to setting timing constraints an
analysing timing results.
Is there any literature or documentation that you could recommend tha
might help me?

Regards,
James


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Tue Sep 27, 2011 12:58 pm   

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594


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