EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

elektroda.net NewsGroups Forum Index - LSI - **HSpice Simulation**

Guest

Mon Oct 17, 2005 1:06 pm

Hey,

I simulated a circuit in Hspice such that the rise time was within

10ns. I designed the layout of the circuit in Magic and extracted to

spice and again simulated in HSpice. There is a difference in the

result of the two simulations. Should there be a diff in the first

place, if yes why should there be a diff?

Thanks,

Haran

PS: In both the cases I added an external load capacitance of 1fF.

Guest

Tue Oct 18, 2005 8:20 pm

What do you mean by different? (i.e. How close?)

Have you exactly created the same circuit. (or close ?)

Are the netlists identical? If not, then the results will be different.

Is the model information of the devices filled in to the same extent?

( i.e. Source & Drain Areas and perimeters, Resistor end effects, etc.

As Hspice (or any analog simulator) is essentially solving a sequence of

equations to an acceptable tolerance using (many) floating point

calculations,

the exact answer arrived at will be (possibly) slightly different with each

difference in the netlist.

It is possible to get (slightly) different answers by just re-ordering the

identical netlist as the tool

does not have to converge to exactly the same value on startup and still

meet the default (or your own)

convergence criterion.

Now, having said all of that, most circuits should approx. simulate the

same, when not exposing the simulators

to ill conditioned inputs. ( Try simulating a series of ideal diodes and

watch it give the simulator fits ... )

-- Gerry

<nkharan_at_gmail.com> wrote in message

news:1129558018.350759.176280_at_g43g2000cwa.googlegroups.com...

Hey,

I simulated a circuit in Hspice such that the rise time was within

10ns. I designed the layout of the circuit in Magic and extracted to

spice and again simulated in HSpice. There is a difference in the

result of the two simulations. Should there be a diff in the first

place, if yes why should there be a diff?

Thanks,

Haran

PS: In both the cases I added an external load capacitance of 1fF.

I simulated a circuit in Hspice such that the rise time was within

10ns. I designed the layout of the circuit in Magic and extracted to

spice and again simulated in HSpice. There is a difference in the

result of the two simulations. Should there be a diff in the first

place, if yes why should there be a diff?

Thanks,

Haran

PS: In both the cases I added an external load capacitance of 1fF.

elektroda.net NewsGroups Forum Index - LSI - **HSpice Simulation**