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how to simulate verilog with rom in modelsim?

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seanzhang
Guest

Thu Aug 12, 2004 2:01 am   



I got error like this in modelsim:
# Loading work.top_tb
# Loading work.top
# Loading work.rom1
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom1' has a `timescale
directive in effect, but previous modules do not.
# Region: /top_tb/top1/rom1_inst
# ** Error: (vsim-3033) D:/my project/FPGA logic/tb1/rom1.v(77):
Instantiation of 'altsyncram' failed. The design unit was not found.
# Region: /top_tb/top1/rom1_inst
# Searched libraries:
# work
# Error loading design

seanzhang
Guest

Thu Aug 12, 2004 2:35 am   



who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most

Petter Gustad
Guest

Thu Aug 12, 2004 9:03 am   



"seanzhang" <sean_at_iron-sword.com> writes:

Quote:
I got error like this in modelsim:
....
Instantiation of 'altsyncram' failed. The design unit was not found.

You need to include the Altera library. You will find this in

[Quartus install directory]/eda/sim_lib/altera_mf.v


Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Jason Zheng
Guest

Thu Aug 12, 2004 5:21 pm   



seanzhang wrote:

Quote:
who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most


module pseudo_rom(addr, data)
input [1:0] addr;
output [15:0] data;

reg [15:0] data;

always @ (addr)
case (addr)
2'b00: data <= 16'h0001;
2'b01: data <= 16'h0002;
2'b10: data <= 16'b0003;
2'b11: data <= 16'b0004;
default: data <= 16'b0001;
endcase
endmodule

Jason Zheng
Guest

Thu Aug 12, 2004 5:23 pm   



Jason Zheng wrote:

Quote:
seanzhang wrote:

who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most


module pseudo_rom(addr, data)
input [1:0] addr;
output [15:0] data;

reg [15:0] data;

always @ (addr)
case (addr)
2'b00: data <= 16'h0001;
2'b01: data <= 16'h0002;
2'b10: data <= 16'b0003;
2'b11: data <= 16'b0004;
default: data <= 16'b0001;
endcase
endmodule
btw, anyone knows the best way to synthesize rom with actel FPGA? I'm

using simplicity

seanzhang
Guest

Mon Aug 30, 2004 2:59 am   



I compile them,but it seems that mif file is not loaded?
how to do this?I am really really puzzled

pablo aimar
Guest

Sat Sep 11, 2004 12:35 am   



"seanzhang" <sean_at_iron-sword.com> wrote in message news:<5397f65aa564b8ca52025903037d7ef4_at_localhost.talkaboutprogramming.com>...
Quote:
I compile them,but it seems that mif file is not loaded?
how to do this?I am really really puzzled


Hi
have a look at coregen documents of xilinx(ram/rom). you have two
types of memory initialization files -- *.mif and *.coe file.
*.mif file is used for simulation
*.coe file for hardwired initialization after programming.

using *.mif is a old approach.

what i did is assign *.coe file in coregen and generate post layout
simulation model and simulate.

or after assign in coregen you can also do functional simulation.

check this and let me know ?

-rao


Guest

Sat Apr 08, 2017 5:12 am   



Em quarta-feira, 11 de agosto de 2004 23:01:18 UTC-3, seanzhang escreveu:
Quote:
I got error like this in modelsim:
# Loading work.top_tb
# Loading work.top
# Loading work.rom1
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom1' has a `timescale
directive in effect, but previous modules do not.
# Region: /top_tb/top1/rom1_inst
# ** Error: (vsim-3033) D:/my project/FPGA logic/tb1/rom1.v(77):
Instantiation of 'altsyncram' failed. The design unit was not found.
# Region: /top_tb/top1/rom1_inst
# Searched libraries:
# work
# Error loading design


If you are using Verilog you have to add the altera_mf library, if you are using VHDL you have to use altera_mf_ver library... just click on Simulate >> Start Simulation >> Libraries. ModelSim does not support .mif, so you have to open it in QuartusII and save as .hex, so that ModelSim can read. You have to put the .hex in ModelSim work directory (type pwd). Now you'll get rid of this 'altsyncram failed' message. If ModelSim starts the memory content with zeroes, try this:
- replace the relative path to the full path of your .hex in the generated ..v memory file
- try this convert_hex2ver.dll approach: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10062000_9191.html


Guest

Sat Apr 08, 2017 5:13 am   



Em quarta-feira, 11 de agosto de 2004 23:01:18 UTC-3, seanzhang escreveu:
Quote:
I got error like this in modelsim:
# Loading work.top_tb
# Loading work.top
# Loading work.rom1
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom1' has a `timescale
directive in effect, but previous modules do not.
# Region: /top_tb/top1/rom1_inst
# ** Error: (vsim-3033) D:/my project/FPGA logic/tb1/rom1.v(77):
Instantiation of 'altsyncram' failed. The design unit was not found.
# Region: /top_tb/top1/rom1_inst
# Searched libraries:
# work
# Error loading design


If you are using Verilog you have to add the altera_mf_ver library, if you are using VHDL you have to use altera_mf library... just click on Simulate >> Start Simulation >> Libraries. ModelSim does not support .mif, so you have to open it in QuartusII and save as .hex, so that ModelSim can read. You have to put the .hex in ModelSim work directory (type pwd). Now you'll get rid of this 'altsyncram failed' message. If ModelSim starts the memory content with zeroes, try this:
- replace the relative path to the full path of your .hex in the generated ..v memory file
- try this convert_hex2ver.dll approach: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10062000_9191.html


Guest

Sat Oct 14, 2017 4:25 am   



you can use quartus to do simulation. The QT internal built-in the altera-modelsim, so you can easily to use the altera library. not affect you use the actel FPGA. You just can do simulation in QT.

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