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HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG

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Anonymous
Guest

Fri Jun 28, 2019 9:45 pm   



There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing this 4x1 mux is used as 32bit image is divided into 8bit. The problem I'm facing is I don't know how to read a single reg in 2 clock cycles i.e. 32bit in one cycle and remaining 32bit in second cycle. I'll be grateful if you can help me out with it. Thankyou.

gtwrek
Guest

Sat Jun 29, 2019 12:45 am   



In article <47eef6e5-1fdf-46ad-81c3-08387dfd526e_at_googlegroups.com>,
Anonymous <bazgha.amin_at_gmail.com> wrote:
Quote:
There is a 64bit input that is stored in register. A single clock cycle can
read 32bits at a time. For implementing this 4x1 mux is used as 32bit image
is divided into 8bit. The problem I'm facing is I don't know how to read
a single reg in 2 clock cycles i.e. 32bit in one cycle and remaining 32bit
in second cycle. I'll be grateful if you can help me out with it. Thankyou.


In FPGA design, one "reads" a 64-bit register just be referencing the
designed signal in HDL. i.e. in verilog:
reg [ 63 : 0 ] foo;
reg [ 63 : 0 ] bar;

always @*
bar = foo;

One can randomly access "foo" (or bar, or any other wire/register) as many
times as you wish. There's no limits on size/etc. (Other than perhaps
FPGA routing/logic resources).

My feeling, however, is you're talking about a software-ish read from an
(unspecified) processor across an (unspecified) bus.

Without more details, we can only guess. But the normal procedure one
follows here, is to simply issue two software read operations. One to
lower half of the 32-bit word, one the the upper half of the 32-bit
word. Some software massaging to correctly organize the 2-independant
32-bit reads into the singular 64-bit software variable.

Fill in some more details, and we can perhaps help you more.

Regards,

Mark

elektroda.net NewsGroups Forum Index - FPGA - HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG

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