How to get integer value for register contents ?

Fri Jan 29, 2010 7:10 am   

Could some Verilog guru please help ? I am passing a 32 bit register
as input to a module. What would be a good way to convert the register
contents to an integer ? Is there some standard Verilog function to do
this, for example, VHDL as 'CONV_INTEGER'. Any hints, suggestions
would be of immense help - thanks in advance for your help.

Fri Jan 29, 2010 7:10 am   

On Thu, 28 Jan 2010 21:10:11 -0800 (PST), Daku <dakupoto_at_gmail.com>
wrote:


VHDL is a strongly typed language so to assign a bit vector (signed or
unsigned) to an integer one has to call the function mentioned above.
Verilog is a weakly typed language so any bit vector can be assigned
to an integer at will without any conversion functions. Assuming
integer is implemented with 32 bits in your simulator (it's supposed
to be at least 32 bits which is fine; anything larger can cause
trouble during the implicit conversion) you will get a meaningful
result.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Fri Jan 29, 2010 7:27 am   

Daku <dakupoto_at_gmail.com> wrote:


Unless I am very confused by your question, there is no such
function in verilog. It just does it. If you want, you can
add 0, which should do it if you were in a case where a 32 bit
register wasn't good enough.

The usual problem with integer is that it is 32 bits when
you might have wanted something smaller. That doesn't seem
to be a problem in this case.

-- glen