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How can I calculate the gate count for a design?

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elektroda.net NewsGroups Forum Index - Synthesis - How can I calculate the gate count for a design?

Lee
Guest

Sun Aug 22, 2004 10:25 pm   



Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.

Thanks

Adrian

ka
Guest

Mon Aug 23, 2004 4:28 am   



On 22 Aug 2004 14:25:25 -0700, yxl4444_at_louisiana.edu (Lee) wrote:

Quote:
Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.

Thanks

Adrian

You can do this by generating an area report (report_area -hier ).
This shows you the area of all blocks in some unit. This unit depends
on the cell library you used. To get the NAND2 count for the design,
you need to find out the size of the 1x drive NAND2 cell and divide
the total size to that number.

Lee
Guest

Mon Aug 23, 2004 3:14 pm   



Hi,

What is the gate in "the gate count" mentioned by papers?NAND or NOR
or Inverter?

If I use the different basic gate, the gate count for a design could
be different. What is the usual way?

Thanks,

Adrian



kal<kal_at_dspia.com> wrote in message news:<c6pii01lp9mvq6n5tchdu57togc8s68g26_at_4ax.com>...
Quote:
On 22 Aug 2004 14:25:25 -0700, yxl4444_at_louisiana.edu (Lee) wrote:

Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.

Thanks

Adrian

You can do this by generating an area report (report_area -hier ).
This shows you the area of all blocks in some unit. This unit depends
on the cell library you used. To get the NAND2 count for the design,
you need to find out the size of the 1x drive NAND2 cell and divide
the total size to that number.


ka
Guest

Tue Aug 24, 2004 4:34 am   



On 23 Aug 2004 07:14:52 -0700, yxl4444_at_louisiana.edu (Lee) wrote:

Quote:
Hi,

What is the gate in "the gate count" mentioned by papers?NAND or NOR
or Inverter?

If I use the different basic gate, the gate count for a design could
be different. What is the usual way?

The gate count is usually NAND2 with a 1x drive.

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